The primary purpose of surface finishes is to prevent oxidation of the copper prior to soldering components.

Back when I held a soldering iron, we used a mixture of tin (63%) and lead (37%) for the solder (Sn63). The boards had the same coating on the plated holes and surface-mount pads. The application for surface mount is referred to as hot air solder leveling (HASL) and applies to any of the available solder types. The beauty of Sn63 is it has a lower melting point and is eutectic. “Eutectic” means the metal solidifies rapidly over a short temperature range. The benefit is fewer disturbed solder joints and good “wetting,” where the surface finish and the solder form a cohesive bond for a reliable connection. You can still buy Sn63 off the shelf at the local electronics store.

On the other hand, lead is a dangerous metal that can cause birth defects and other health issues. The Europeans took the vanguard with the RoHS initiative. If you want to sell electronics products to consumers, the lead content must be the minimum possible – not eliminated entirely but found primarily as a trace element within chips.

SAC (Sn-Ag-Cu): a heroic alloy. Metallurgists all over the world looked for replacement formulas. Tin is still viable and is generally mixed with small amounts of silver and other elements such as antimony, copper or bismuth. Tin makes up the bulk of the alloy, typically around 95% to 99.3%. If pure tin was used, the results could be problematic. Tin whiskers from dendritic growth present a shorting risk.

FIGURE 1. Pure, non-alloyed metals exhibit crystalline growth as the metal forms branches over time. Environmental conditions can aggravate the process. (Source: NTS Corp.)

Without lead, tin has a much higher melting point and does not solidify as quickly. The double-complication requires a dielectric material that can withstand the higher temperatures without breaking down.

The maximum working temperature of the material is one of the primary selling points. It is known as the glass transition (Tg) temperature. The materials we used in the old days did not stand up to the process, so the entire PCB material set had to be seriously upgraded. Going lead-free raised the reflow temperatures considerably. Boards and components alike have gone green since then.

Exemptions exist where tin-lead is still allowed. Spacecrafts that will eventually burn up on reentry are one such exemption. The goal of RoHS is to reduce the amount of lead that goes into the landfill. Provided the company can certify all its products will be returned to the factory for proper disposal, Sn63 coatings on the PCB are permissible. Obviously, consumer products do not get such an exemption.

ENIG: the gold standard. While tin-silver plating is still viable, the “gold standard” is gold. The mainstream alloy is immersion gold over electroless nickel over copper, or ENIG for short. The reason this is a preferred plating is the downstream process of assembly is more boring without the likelihood of tin whiskers. We like it to be boring when it comes to making goods. Those who study S-parameters also have a fondness for the consistency of ENIG finishes.

This plating is primarily aimed at high-density interconnect fabricators. The process can yield a solderable footprint with via-in-pad situations. Fine-pitch BGAs and other shrunken circuits require microvias. Plating with ENIG will likely improve yields due to the land patterns coming out flatter than with other types of plating. It’s also a go-to finish for flex circuits. It plays well with solder mask, making a good base for the following layer.

FIGURE 2. ENIG finish with through-hole vias and surface-mount components.

A note on “black pad”: This process defect was a hot topic for a few years. That time has passed. The fabricators worked out the right amount of phosphorus in the nickel to prevent the defect that was more than a cosmetic issue. That concern was laid to rest.

ENIPIG: not too hard, not too soft. Electroless nickel, immersion palladium, immersion gold adds palladium as a physical barrier between nickel and gold. That opens up the process. The main benefit to ENIPIG is the outer layer of gold is soft enough to be a good candidate for wire bonding, while still working well for soldering. The alternative for chip-on-board is a selective soft gold finish: the do-everything finish.

When selecting the correct finish, know the constraints. While ENIPIG has an upcharge, it’s not as expensive as soft gold or hard gold when used in combination with medium gold. Note medium hardness is geared for solderability, while hard gold creates a more durable contact surface for “gold finger” edge connectors. To meet the specification for HDMI, the gold fingers must withstand 10,000 insertion/extraction cycles.

OSP: a minimalist approach. Organic solderability protectant is a very thin coating consumed by the reflow process. In the factory, we had to be aware of the date codes on boards with OSP. You don’t want old boards with this coating.

During design, when reaching back to padstack definitions, the designer must coordinate something extra when using OSP. We had to include a paste stencil opening on our test points when the boards had OSP, or the test points would end up with bare copper. The exposed copper will tarnish over time. None of the other finishes have this requirement.

An IPC specification for OSP (IPC-4555) is on the horizon. Per a report on this publication’s website in August 2020, “The goal is to develop performance specifications for high-temperature OSPs, defined as capable of withstanding up to two IR reflows in conjunction with tin-silver-copper (SAC) or tin-bismuth (SnBi) alloys at a peak temperature of 245°-250°C and showing the same wetting balance results at three reflows as zero, with a maximum 20% drop.”

This is good news since OSP is well-suited to mass production runs. The micro-thin coating does not hinder solderability. The cost is low, along with the shelf-life. Organic solderability protectant has been around for quite some time with proprietary processes, so it will be beneficial to have a performance standard across the board. 

JOHN BURKHERT JR. is a career PCB designer experienced in military, telecom, consumer hardware and, lately, the automotive industry. Originally, he was an RF specialist but is compelled to flip the bit now and then to fill the need for high-speed digital design. He enjoys playing bass and racing bikes when he's not writing about or performing PCB layout. His column is produced by Cadence Design Systems and runs monthly.

A board’s level of technology should dictate how often to expect imperfections.

One of the most common questions I get from PCB buyers is, “How many X-outs are acceptable?” Some might say receipt of a PCB manufacturing panel or array with any X-outs indicates the supplier cannot maintain a high level of quality.

This is not necessarily the case.

An X-out occurs when a defective board in an array or manufacturing panel of like PCBs has been shipped. The board is literally marked with an X in permanent marker to signify it is flawed.

While a panel or array with zero X-outs is ideal, the board’s level of technology should dictate how often to expect this kind of perfection. If the board is a single-, double- or easy four-layer item, then a PCB buyer should expect – in fact, should demand – the manufacturer deliver panels free of defective boards.

However, if it is a higher technology – such as an HDI design – scrap will happen in every manufacturing lot. To expect otherwise is not realistic.

Any experienced PCB supplier knows this custom-made item – requiring more than 100 different manufacturing processes – will have a board (or boards) with some sort of rejectable imperfection in every manufacturing lot released to the floor. To address this issue, before the board order hits the production floor, the fabricator will release an overage, depending on the board’s technology, to ensure its manufacturing processes yield the number of boards required to fulfill an order.

The more high-tech the board is, the more overage may be necessary to account for any fallout.

For example, let’s say 1,050 pieces are released to meet an order requiring 1,000 individual boards. In this case, the manufacturer decides a board’s technology will require only an additional 5% in materials overage.

At final QC, the vendor then finds 32 pieces (or about 3%) did not make it through the manufacturing process for various reasons. Those bad boards are scrapped.

Because a 5% overage was produced, 1,018 pieces are good. So, the 1,000-piece order is shipped as promised, and the additional 18 pieces are put into finished spares. Everyone is happy, with most customers not paying any attention to the fallout that occurred within that overage amount.

Sometimes, though, having PCBs delivered in an array or panel format might highlight manufacturing challenges, especially when a customer has a “No X-out” policy.

If you put that same order in a four-up array, then 250 arrays would need to be perfect to meet the 1,000-piece requirement. Based on those numbers for that technology, the manufacturer could expect the same percentage of fallout. But boards found at final QC that don’t pass muster are “connected” to three pieces that passed with flying colors. This means 32 arrays with an X-out or 128 pieces total (32 x four-up) are not allowed to ship, regardless of their quality.

The vendor must release more overage (about 15%, or 152 pieces, because it’s a four-up array) to accommodate the normal fallout that occurs during the manufacturing process for arrays that can’t have any X-outs.

Whether your company accepts X-outs or not should be detailed in your firm’s PCB fabrication specifications. This information will guide your board suppliers on how much material (overage) they must release – based on their technical capabilities – to fulfill an order.

Here is an example of an EMS company’s X-out policy that is clearly spelled out:

“X-outs are allowed. However, not more than 20% of the PCBs in the array can be X’d-out, and no more than 10% of the arrays to be shipped may contain an X-out.”

This means if you have, say, a 2,000-piece order manufactured in a 10-up panel requiring 200 arrays to be received, the most you should receive is 20 panels that contain no more than two X-outs each.

Your fabrication specs should also state how X’d-out panels are to be received to avoid causing headaches for both receiving and production departments. A statement like this works:

“X’d-out arrays are to be segregated and identified accordingly at time of shipment.”

PCB buyers should keep in mind the amount of real estate needed for perfect arrays (no X-outs) means the overall cost of the board will be higher. The adage about not allowing the perfect to become the enemy of the good is applicable here.

Before your company sets its X-out policy, sit down with your manufacturing department. There are ways for an assembler to handle manufacturing panels with X-outs, but the department responsible for shipping quality, finished assemblies should have final say on X-outs.

A rigid “No X-out” policy will likely cost you more without improving the PCB manufacturing process. In most cases, a more flexible approach is warranted.

GREG PAPANDREW has more than 25 years’ experience selling PCBs directly for various fabricators and as founder of a leading distributor. He is cofounder of Better Board Buying (boardbuying.com); greg@boardbuying.com.

Register now for PCB East, the largest electronics technical conference and exhibition on the East Coast. Coming in April to Marlboro, MA.

As governments realize the importance of investing in domestic manufacturing, opportunities are coming for EMS firms and PCB fabricators.

It takes time to gain perspective, especially perspective on the industry you are immersed in. In my case, it’s been 30 years since I entered the printed circuit board market. During the first six or seven years, it was heady, upbeat times in North America. Growth was a bounty supporting hundreds of domestic fabricators. Materials, supplies and capital equipment were made “locally” in North America. Then, around the new millennium, everything changed.

Suddenly, work headed to Asia, and fabricators contracted at an unprecedented scale to fewer than 200 within a few short years. The collateral damage was a collapse of materials, supplies and capital equipment companies that supported the industry. Even worse was the exodus of skilled talent who sought careers in more promising industries and never looked back. The relatively few companies that survived did so by hunkering down, focusing on a niche, and investing in only the equipment they needed to support their business base, in some cases taking draconian steps that worked short term but eventually led to their demise. Over the first decade-plus of the new millennium, it was depressing to be a North American circuit board fabricator.

However, times change, and with that change, opportunities emerge – finally!

After decades of ignoring reality – and for a variety of reasons and events, many of which have nothing to do with printed circuit boards, or even electronics – government and industry leaders are “shocked” to learn so much of North America’s manufacturers are no longer globally competitive and how much more capability and capacity is required for economic and military security. Now that they understand the need to invest in manufacturing, more specifically in electronics manufacturing – everything from chips to bare circuit boards and substrates – opportunities for the North American PCB industry finally may be knocking.

Do we open the door and take full advantage, or ignore it and squander our chance?

To take advantage of the current momentum to expand and enhance North American capabilities and manufacturing capacity may require a radical rethinking, or at least retraining, in how we as an industry operate. The entire risk/reward equation in particular needs to be revisited. After nearly 20 years of operating in a hunkered-down mode to mitigate risk and maximize reward, many in our industry may need to be retrained to break old habits and embrace a paradigm shift the opportunities of the future offer.

The first step toward taking advantage of new opportunities may be a brutally honest self-evaluation of what your company does, for whom, and with what resources. Most important is understanding what government or “C-suite” investment in electronics technology may look like and how that will impact your customers. As an example, if chip plants are built in North America, what other electronics manufacturing may now become more cost-effective if done closer to those plants vs. overseas. And, what printed circuit board technology will that increased demand for capacity impact?

With investment in more advanced technology, will new materials and the processing knowhow and equipment be outside current capabilities or comfort zones? Discussions with material suppliers should include a dialogue on what to be aware of; begin experimenting to be better prepared.

If the gap in North American electronics capability points to a specific type of printed circuit board technology that will be in especially high demand, that may be the place to consider increasing capital investment to either add capacity, enhance capability or broaden product offerings to include the growth opportunity. This review should include an estimated capital equipment budget and supporting cash flow, as well as a reality check with current customers to understand if their products and purchasing demands may also be impacted and shifting.

When demand increases, what type of employees will your company need to hire? This leads to workforce development opportunities that currently exist, and in the next few years will expand with an increase in qualified people seeking jobs in electronics. More important, with the emphasis on investing in new capabilities, what talent gap might you have that would prevent being able to produce a new technology? Getting involved now may be the best way to ensure having qualified talent when needed.

To take advantage of any opportunity that a reinterest in North American electronics manufacturing may present, it is essential to stay informed and get your team ready. Nothing will happen overnight, but it will happen more quickly than anyone who has become comfortable in the current industry paradigm imagines. We all need to be aware significant new opportunities are finally on the horizon.

After so long operating in a contracting industry segment, we in North America cannot afford to let the coming opportunities be squandered. Opportunity for growth is knocking for us all. 

PETER BIGELOW is president and CEO of IMI Inc.; pbigelow@imipcb.com. His column appears monthly.

How using a thinner stencil corrected transfer efficiency.

SMT specialists are intimately familiar with the guiding rule of stencil printing: the area ratio. The correlation between stencil aperture dimensions and the predictability of solder paste transfer efficiency is well understood, and IPC has standardized design guidelines outlining ideal conditions. The accepted area ratio for maximum transfer efficiency is approximately 0.60, which is a function of the aperture open area and aperture wall area (stencil thickness). When the area ratio falls below the recommendation, challenges arise.

Reaffirmation of the relevance of the area ratio rule occurred recently when our company was asked to analyze a customer assembly where bridging was observed. The printing dimensions of the PCB’s bridging area were tight. The 01005 apertures measured 200µm x 200µm, the stencil thickness 80µm and the interspace about 150µm. So, while not at the bleeding edge like some newer-generation designs, the board was nevertheless challenging. With these aperture dimensions, the area ratio was an acceptable 0.63. The volume of paste on pad was 2.08 nanoliters (NL), and the standard deviation was less than 10%, but SPI analysis revealed bridging.

For its part, the customer had logically attempted to lessen the bridging propensity by narrowing the aperture width to reduce the amount of solder paste being transferred onto the pad. Unfortunately, doing so resulted in conflict with the area ratio rule, and taking this route ultimately impacted repeatable transfer efficiency.