Circuits Assembly Online Magazine - A Study of 0201s and Tombstoning in Pb-Free Systems

News

A comprehensive DoE finds paste and placement offsets the top contributor to defects.

The mechanics of tombstoning are based on molten solder wetting forces, component mass and geometry. If solder paste under one termination melts and starts wetting to the termination before the other side does, the wetting action force can pull that component up on its end. Typically, the smaller and lighter the component is, the more susceptible it is to tombstoning.

Factors in tombstoning can be classified into two main categories: design-related (pad design; pad definition, mask or metal; thermal balance between pads; unfilled microvias in the pads) and process-related factors (numerous, and often difficult to quantify). Many DoEs have been performed and published on the topic, often focusing on best practices for design and assembly.

Most 0201 assembly processes were optimized prior to the transition to Pb-free processing. Increasing production of Pb-free products and the associated tighter process windows now dictate a reassessment of the key parameters that can affect tombstone formation.

Experimental Design

A review of published studies and high-volume production experiences uncovered 49 potential parameters that can influence tombstone defects. The investigators then used a cause-and-effect (C&E) matrix approach (rating influence 0, 3 or 9) to identify the following 12 parameters as the most influential:

Padstacks. This includes pad sizes and spacing between pads. All pads were non-solder mask defined (NSMD), and did not have solder mask between the pads. Four sizes were considered. Three are considered public domain; the fourth is considered proprietary.
Solder paste volume. Stencil apertures were designed at 70% and 100% area of each pad size. A 70% area represents the least acceptable transfer efficiency; 100% area represents the best possible transfer efficiency. For the feature sizes used in this study, apertures designed at 70% released about 50% of the paste from the apertures, and apertures designed at 100% released about 60%. The transfer efficiencies vary with each solder paste and the different apertures’ area ratios.
Print offsets. To simulate alignment error, stencil apertures were designed at nominal pad position and with 0.1 mm offsets in both X and Y directions, for a total of four combinations: (0,0; 0,0.1; 0.1,0.1; and 0.1,0.1).
Component type. Resistors and capacitors were used to capture effects of component height and number of sides per termination.
Orientation. Components were mounted at 0 and 90°.
Reflow profile. Straight ramp and high soak profiles were used.
Reflow atmosphere. Air and 100 ppm N2 atmospheres were applied in soldering cycles.
Placement offset. Components were placed at two positions: their nominal 0, 0 (CAD) position, and a 0.1, 0.1 mm offset in X and Y concurrently.
Solder paste. In Phase 1 of the study, three solder pastes were used: no-clean SnPb, no-clean SAC 305, and water washable SAC 305. In Phase 2, the number of pastes was expanded to seven.
PWB final finish. In Phase 1, organic solderability preservative (OSP) was used. In Phase 2, OSP and electroless nickel-immersion gold (ENIG) finishes were used.

The experiment was partitioned into two phases. The experimental matrix for Phase 1 is shown in Table 1. Factors listed in the top half were designed into the test vehicle (Figure 1). Factors in the table’s bottom half were varied during the assembly process.

Test vehicle. The TV contained 48 individual test cells. Four different pad designs were used, each appearing twelve times on the test vehicle, six times per row of cells on two rows. Each cell had 50 resistors and 50 capacitors oriented at 0 and 90°, a total of 200 per block (Figure 2). Eight cells per padstack were assembled per board, for a total of 1600 placements per padstack per board. In Phase 1, all four padstacks were used, resulting in 6400 component placements per board.

Stencil design. To achieve all combinations of aperture reductions and offsets in a single print, the following modifications were made to the stencil design. From left to right, of the six columns of test cells, the first two columns had apertures reduced to 70% of their pad area; the middle two were not populated, and the last two had no aperture reductions applied. Within each group of aperture reductions, the test cells were divided into four segments, with each segment having a different aperture alignment offset.

Using the design shown in Figure 3, each combination of padstack design, aperture reduction and alignment offset appears twice per board. Two replicates were used, so each combination was assembled in four test cells.

Assembly. Upon receipt of the components, samples were inspected, which included dimensional measurements and XRF screening to ensure lead was not present in the system. All TVs were assembled in the Jabil Circuit Advanced Manufacturing Technology laboratory in St. Petersburg, FL, using the following equipment:

MPM Ultraprint 3000 stencil printer.
Koh Young KY3030-VAL paste measurement system.
Fuji AIM pick-and-place.
Vitronics-Soltec XPM2 reflow oven.
Vi Technology Vi3K2 AOI.
Phoenix Nanomex X-ray inspection.

Stencil printing. The investigation included high and low paste volume settings. In order to achieve two levels of paste volume, the stencil apertures were reduced. To identify the most appropriate aperture reduction, a prescreening study was performed. Stencil apertures were sized at 100%, 80% and 60% of their corresponding pad areas for all four footprints. It was determined through the prescreening DoE that 70% pad area, or 30% reduction, would be appropriate for the low setting. 100% pad area and 70% pad area equate to transfer efficiencies of roughly 60% and 50%, respectively, and varied slightly with the individual solder pastes and aperture designs.

Stencils used in the study were electroformed nickel with 125 µm (0.005") foils. All solder pastes were printed at the same parameters: 2"/sec. squeegee speed, 1.25 lb./in. squeegee pressure, slow separation speed.

Paste volume measurement. The SPI was used to measure paste volume deposition in all phases of the experiment. This proved to be especially useful in the prescreening experiment to determine the appropriate aperture reduction to apply to the stencil design.

The equipment employs a proprietary Phase Shift Profilometry (PSP) algorithm using a moiré light projection technique. This technique uses opposing dual-source LED lighting to capture eight images (four from each side) for every solder deposit. Using a reconstruction algorithm, the eight images are combined to form a 3-D model of the solder deposit. The dual source lighting technique is advantageous because it reduces the shadowing effect associated with single light source systems. With a pixel size of approximately 20 x 20 µm, it is important to have the most accurate information possible, particularly with the 0201 deposits in the size range of 0.010"-0.019".

To ensure system capability, a rotational Gage R&R was performed using Minitab’s crossed ANOVA method. The Total Gage R&R figure needs to be below 30 for the system to be used as an acceptable measurement instrument. Using a process tolerance window of +/-25%, the Total GRR for the test vehicle was around 20, with a repeatability figure below three. The cycle time for the equipment to measure nearly 20,000 solder deposits was approximately 55 sec.

Placement. The two-gantry, four-head placement machine handles devices from 0201s to 74 mm square. It has 180 feeder inputs and can feed from tape and reel, strip tape, sticks, and matrix trays. Its speed is rated at 20,300 cph. The machine was installed in the laboratory and calibrated prior to the test. A GR&R study was not performed prior to the test.

Reflow soldering. Six thermocouples were used to profile the assembly. Four were attached to the topside, two to the bottom (Figure 4). The reflow profiles depicted in Figures 5 through 8 were developed on unpopulated PWBs.

AOI. The AOI was used to inspect boards pre- and post-reflow. Starting from the same CAD information, both programs were generated using the equipment manufacturer’s standard library. In the data presented below, the system was used to detect full and partial tombstones, and positional errors in X, Y and theta. For this test, the equipment was installed and calibrated by the manufacturer; a GR&R study was not performed prior to the execution of the experiment.

X-ray inspection. The x-ray was used to inspect for solder balls. PWBs were x-rayed, the resulting images visually interpreted, and the solder ball count manually recorded for each quadrant of the PWB. Solder ball defects were recorded for each PWB, but not uniquely associated with individual components.

Data Collection

Defects were classified as:

Full tombstones, where the component stands completely up on one end at approximately a 90° angle to the PWB plane.
Partial tombstones, also known as drawbridges, where the component is soldered at one termination but not at the other and stands at an angle between 0° and 90° to the PWB plane.
Non-wets, where the component remains planar to the board surface, but solder has not adequately wetted to one or both of the terminations.
Positional errors, in which one or both component terminations are offset from the pad edge by more than 50% of the termination width in X, Y or theta.
Solder balls, or spheres of solder that remain after soldering. The minimum size recorded was that which was visually perceptible on x-ray images, approximately 75 to 100 µm (0.003"-0.004") in diameter. Workmanship criteria such as locations relative to the components or levels of encapsulation were not recorded.

Examples of the defect modes are depicted in Appendix A.

Results and Discussion – Phase I Data

Defect overview. Defect rates for six specific failure modes were recorded. The overall defect rate for the experiment was 11,823 ppm. The defects breakdown is shown in Figure 9.

Solder balls were the most commonly observed phenomenon, but it should be noted that although they are all reported as defects in this study, not all solder balls observed would necessarily represent defects in a production environment. Some would be considered defects; others would not. For example, solder balls larger than the minimum spacing of the surface-mount leads and not entrapped or encapsulated enough (by no-clean flux residue) to prevent dislodging in their service environments would be considered defects. Solder balls that do not violate minimum spacing requirements or those judged to be adequately entrapped would not. Inspection criteria vary by product, but in general, solder ball formation is indicative of coalescence properties during reflow. Because solder balls showed such a considerable response in the experiment, but workmanship standards vary widely, defect rates are reported with and without the inclusion of solder balls. When reviewing the results, solder balls should not be considered as absolute defects, but as relative indicators of coalescence.

Positional errors in the X and Y directions were observed with the same frequency as solder balls. The other failure modes observed (in order of declining frequency) were non-wets, full tombstones and partial tombstones. Although these five failure modes were differentiated for the purposes of this investigation, from a production perspective they share a common characteristic: They all require rework.

Tombstone formation was the focus of the study; the data were statistically analyzed for the input variables’ effect(s) on tombstoning rates. The top four contributors to tombstoning included three main effects and one interaction. The interaction between paste offset in the X direction and placement offset (in both X and Y) had the largest overall effect on tombstoning rates. When the effects of paste and placement offsets were removed, the overall defect rate dropped from 11,823 ppm to 2,513 ppm including the solder balls, or from 7,845 ppm to 156 ppm excluding the solder balls (Figure 10).

It is clear that eliminating unnecessary offsets in printing and placement removes an enormous source of defect generation, not only for tombstones but all defect modes. The placement offsets used in this study were representative of conditions commonly found in an out-of-control production environment. The 0.1 mm (0.004") offset on placement coordinates is considered to be within the actual placement capability of many high-speed chip placement machines. Although the paste offset of 0.1 mm (0.004") is larger than the typical positional error on most stencil printers, the source of PWB-stencil misregistration is typically not a result of the equipment, but of either poor setup or alignment issues created by dimensional inaccuracy of the PWB or stencil.

It should be noted that the equipment used in these experiments was subject to manufacturers’ regular calibration procedures with no special tuning. GR&R studies were not performed on the printer or placement machine prior to the execution of the tests. Actual print alignment and placement accuracy are assumed to be within the manufacturer’s specifications and exhibit typical positional drift from programmed positions within these specifications.

Two placement offset cases were studied: nominal (0,0) and +0.1 mm (4 mil) in both X and Y directions concurrently (+0.1, +0.1). Placement offsets were not subdivided into individual axis shifts (0, +0.1) and (+0.1,0), but print alignment offsets were performed with all four combinations. The combination of paste offset in X with placement offset had a tremendous effect on defects, but the combination of paste offset in Y with placement offset did not. The offset in X was in the positive direction, which is also the leading edge of the device as it enters the reflow zone. The effect witnessed here is likely similar to the effect of component orientation. Note that offsets were not tested in opposing directions, i.e. paste in negative X and placement in positive X and Y or vice versa, but it is assumed that it would hurt the tombstoning rates rather than help them.

The remainder of variables that exhibited large influences on tombstoning were singular or main effects, and not as dramatic as the combined effect of the paste and placement offsets. The second most influential factor was component type. Capacitors exhibited a defect rate of 15,996 ppm (14,316 ppm excluding solder balls), while resistors exhibited a defect rate of 7,650 ppm (1,374 ppm excluding solder balls) (Figure 11).

Capacitors consistently showed higher defect rates in all categories except solder balls. The main differences between capacitors and resistors are their heights and termination geometries. Capacitors are 25% taller than resistors, and have a higher center of gravity, which can make them more likely to yield to wetting forces that cause tombstones.

Resistors showed three times the solder ball rate of capacitors. Regardless of whether certain solder balls are considered defects, the fact that resistors showed three times the incidence rate indicates they are more susceptible to coalescence issues and solder balling defect modes, likely because of their three-sided termination design, which has less surface area to draw molten solder than similarly sized capacitors (Figure 12).

The third most common effect was that of orientation. Components oriented at 0°, or parallel to the direction of travel through the oven, exhibited a defect rate of 15,046 ppm (11,699 ppm excluding solder balls), while components oriented at 90°, or perpendicular to the direction of travel, exhibited a defect rate of 8600 ppm (3,991 ppm excluding solder balls). The results are shown in Figure 13.

The components oriented perpendicular to the direction of travel showed much fewer defects than those oriented parallel to the direction of travel, presumably due to thermal gradients across the component. When a component is oriented at 90°, both terminations enter reflow at approximately the same time. When a component is oriented at 0°, the leading termination enters reflow before the trailing termination.

The paste offset in the positive X direction was 0.1 mm (0.004"). Similar paste offsets in the Y direction did not show a significant impact on defect rates. This behavior may be similar to, or exacerbate the effect of, component orientation on the time differential reaching reflow temperatures.

The fourth largest effect was that of reflow atmosphere. Overall, air atmospheres were associated with defect rates of 18,581 ppm (11,172 ppm excluding solder balls), while the inert environments were associated with 5,065 ppm (4,518 ppm excluding solder balls). The results, shown in Figure 14, are split. Nitrogen environments produced more tombstone defects, but less positional and wetting defects. The nitrogen environment also minimized solder balls formation when compared to air, indicating improved coalescence. Overall, nitrogen environments produced fewer defects than air, but the impact on total defect reduction was not as large as the one provided by print and placement controls.

Solder Paste Type Effect

Figure 15 shows defect rates for each solder paste type. Of the three paste types, the no-clean SnPb paste produced the fewest overall defects, a total of 4,768 ppm (3,679 excluding solder balls). The no-clean Pb-free paste more than doubled that defect rate, with 12,637 ppm (4,697 excluding solder balls). Solder balls were the most common issue for this paste, accounting for almost two-thirds of the recorded defects. Excluding the solder ball count, the defect rates for no-clean SnPb and Pb-free were not extremely different. The water-soluble Pb-free paste had the highest defect rate at 18,154 ppm (15,459 excluding solder balls). When the key factors of print and placement offsets are removed, the defect rate drops dramatically for all paste types (Figure 16).

The defect rates for no-clean SnPb, no-clean SAC 305 and water-washable SAC 305 drop to 625, 4,297 and 2,617 ppm respectively. Again, the vast majority of the recorded defects are solder balls; excluding them from the calculations reveals defect rates of 78, 39 and 352 ppm for each type of solder paste, averaging 156 ppm overall. Regardless of how the data are analyzed, the positive effect of controlling the print and placement process cannot be overlooked.

Padstack Effect

Of the four different padstacks used in the experiment, three were suggested by IPC-7351. Their designations and dimensions are shown in Tables 2 and 3. Padstack results are shown in Figure 17. The largest footprint, IPC-M, resulted in the fewest defects, 4,271 ppm (2,904 excluding solder balls). The medium-sized footprint, IPC-N, showed higher overall defect rate, 5,690 ppm, but excluding the solder balls, it actually performed slightly better than the larger one, at 2,161 ppm. Given that the main purpose of using 0201 components is to more densely populate the PWB, the medium-sized footprint may be the better choice when deciding the tradeoff between design functionality and manufacturability. The smallest padstack demonstrated the highest defect rate at 22,786 ppm (16,003 excluding solder balls).

Conclusion

Conditions varied in this phase of the experiment were component type, padstack, paste volume, paste offset, placement offset, reflow profile and reflow atmosphere. The largest contributor to defect generation was the combination of 0.1 mm (0.004") paste offsets in the X direction and concurrent 0.1 mm placement offsets in X and Y directions. In descending order of influence, the next three major factors were component type, orientation, and reflow atmosphere.

Of the top four factors, two cannot be controlled by the assembler. Component type and orientation are characteristics of the circuit design that are not likely to be changed. The reflow atmosphere may or may not be controllable, as the availability of nitrogen is limited by geographic location and cost sensitivity of the end product. The most predominant factor, however – the print and placement offsets – are almost completely controllable at the assembly level. The impact of removing mechanical slop from the assembly process brought the overall defect rates from 11,823 to 2,513 ppm, or from 7,845 ppm to 156 ppm excluding the solder ball count.

Both offset conditions can be addressed with ordinary process control methods. Machine repeatability can be measured through capability studies; positional accuracy can be addressed by calibration, and stencils/placement programs can be scaled to compensate for PWB positional inaccuracies. It is an accepted notion that process control improves yield performance, and that as feature sizes get smaller, controlling key parameters becomes increasingly important. The dramatic effect of the simulated “sloppy” print/place process on all defect modes demonstrates the need for process controls.

Of the three paste types, the no-clean tin-lead produced the least amount of overall defects, followed by no-clean Pb-free and water-washable Pb-free. Under controlled print and placement conditions, both no-clean pastes produced defect levels of less than 100 ppm, regardless of atmosphere, profile, or padstack.

Of the four pad stacks, the largest produced the least defects, with the mid-sized pads running a close second. The smallest pad showed over four times as many defects as the largest or mid-sized pads.

Bibliography

D. Baldwin et al, “Designing a High-Yield 0201 Assembly Process for New Product Introduction,” SMTA International Proceedings, September 2002.
J.M. Peallat and M. Norris, “AOI: Facing the Challenges of 0201,” SMTA International Proceedings, September 2002.
M. Wang, et al, “PCB Design Optimization of 0201 packages for Assembly Processes”, Telecom Hardware Solutions Conference Proceedings, May 2002.
D. Geiger et al, “Process Characterization of PCB Assembly Using 0201 Packages with Lead-Free Solder,” Nepcon West Proceedings, December 2002.
B. Huang and N.L. Lee, “Conquer Tombstoning in Lead-free Soldering,” IPC Apex Proceedings, February 2004.
S. Lu et al, “Yield Enhancement and Yield Modeling from Mass Reflow Process of 0201 Components,” Journal of the SMTA vol. 17, no. 4, October 2004.
IPC-A-610D, “Acceptability of Electronic Assemblies,” February 2005.
IPC-7351A, “Generic Requirements for Surface Mount Design and Land Pattern Standard,” February 2007.

Ed.: This article was published at SMTA International in September 2007 and is reprinted here with permission.

Paul Neathway, Andrew Butterfield, Quyen Chu, Nick Tokotch and Robert Haddick are with Jabil (jabil.com). Jean-Marc Peallat is with VI Technology (vitechnology.com). Chrys Shea and Prashant Chouta are with Cookson Electronics (cookson.com); cshea@cooksonelectronics.com.