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The defect rates for no-clean SnPb, no-clean SAC 305 and water-washable SAC 305 drop to 625, 4,297 and 2,617 ppm respectively. Again, the vast majority of the recorded defects are solder balls; excluding them from the calculations reveals defect rates of 78, 39 and 352 ppm for each type of solder paste, averaging 156 ppm overall. Regardless of how the data are analyzed, the positive effect of controlling the print and placement process cannot be overlooked.

Padstack Effect

Of the four different padstacks used in the experiment, three were suggested by IPC-7351. Their designations and dimensions are shown in Tables 2 and 3. Padstack results are shown in Figure 17. The largest footprint, IPC-M, resulted in the fewest defects, 4,271 ppm (2,904 excluding solder balls). The medium-sized footprint, IPC-N, showed higher overall defect rate, 5,690 ppm, but excluding the solder balls, it actually performed slightly better than the larger one, at 2,161 ppm. Given that the main purpose of using 0201 components is to more densely populate the PWB, the medium-sized footprint may be the better choice when deciding the tradeoff between design functionality and manufacturability. The smallest padstack demonstrated the highest defect rate at 22,786 ppm (16,003 excluding solder balls).

Conclusion

Conditions varied in this phase of the experiment were component type, padstack, paste volume, paste offset, placement offset, reflow profile and reflow atmosphere. The largest contributor to defect generation was the combination of 0.1 mm (0.004") paste offsets in the X direction and concurrent 0.1 mm placement offsets in X and Y directions. In descending order of influence, the next three major factors were component type, orientation, and reflow atmosphere.

Of the top four factors, two cannot be controlled by the assembler. Component type and orientation are characteristics of the circuit design that are not likely to be changed. The reflow atmosphere may or may not be controllable, as the availability of nitrogen is limited by geographic location and cost sensitivity of the end product. The most predominant factor, however – the print and placement offsets – are almost completely controllable at the assembly level. The impact of removing mechanical slop from the assembly process brought the overall defect rates from 11,823 to 2,513 ppm, or from 7,845 ppm to 156 ppm excluding the solder ball count.

Both offset conditions can be addressed with ordinary process control methods. Machine repeatability can be measured through capability studies; positional accuracy can be addressed by calibration, and stencils/placement programs can be scaled to compensate for PWB positional inaccuracies. It is an accepted notion that process control improves yield performance, and that as feature sizes get smaller, controlling key parameters becomes increasingly important. The dramatic effect of the simulated “sloppy” print/place process on all defect modes demonstrates the need for process controls.

Of the three paste types, the no-clean tin-lead produced the least amount of overall defects, followed by no-clean Pb-free and water-washable Pb-free. Under controlled print and placement conditions, both no-clean pastes produced defect levels of less than 100 ppm, regardless of atmosphere, profile, or padstack.

Of the four pad stacks, the largest produced the least defects, with the mid-sized pads running a close second. The smallest pad showed over four times as many defects as the largest or mid-sized pads.

Bibliography

1. D. Baldwin et al, “Designing a High-Yield 0201 Assembly Process for New Product Introduction,” SMTA International Proceedings, September 2002.
2. J.M. Peallat and M. Norris, “AOI: Facing the Challenges of 0201,” SMTA International Proceedings, September 2002.
3. M. Wang, et al, “PCB Design Optimization of 0201 packages for Assembly Processes”, Telecom Hardware Solutions Conference Proceedings, May 2002.
4. D. Geiger et al, “Process Characterization of PCB Assembly Using 0201 Packages with Lead-Free Solder,” Nepcon West Proceedings, December 2002.
5. B. Huang and N.L. Lee, “Conquer Tombstoning in Lead-free Soldering,” IPC Apex Proceedings, February 2004.
6. S. Lu et al, “Yield Enhancement and Yield Modeling from Mass Reflow Process of 0201 Components,” Journal of the SMTA vol. 17, no. 4, October 2004.
7. IPC-A-610D, “Acceptability of Electronic Assemblies,” February 2005.
8. IPC-7351A, “Generic Requirements for Surface Mount Design and Land Pattern Standard,” February 2007.

Ed.: This article was published at SMTA International in September 2007 and is reprinted here with permission.

Paul Neathway, Andrew Butterfield, Quyen Chu, Nick Tokotch and Robert Haddick are with Jabil (jabil.com). Jean-Marc Peallat is with VI Technology (vitechnology.com). Chrys Shea and Prashant Chouta are with Cookson Electronics (cookson.com); cshea@cooksonelectronics.com.

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