Compensating for PWB positional inaccuracies in 0201s.

For the past 18 months, I’ve had the pleasure of working with a group of very talented people on an experiment to characterize 0201 behavior in a Pb-free soldering environment and compare it to that of a SnPb soldering environment. We had a lot of data to crunch, but when all was said and done, the results were clear. The biggest influence on all 0201 defects was the misregistration of solder paste prints and component placements. If we want to assemble these miniature devices, the most important thing we can do is get our assembly process mechanics under control.

I had to ask, was this too obvious a conclusion? We know that the smaller the device or finer the pitch, the tighter the process needs to be. But exactly how tight is not often quantified. So I took a closer look at some numbers associated with this test. Our experiment considered print and placement registration of +/-0.002" (normal process drift for this equipment) as the in-control scenario and programmed offsets of 0.004" to simulate the out-of-control scenario. If the in-control process lands within +/-0.002" of nominal, is a 0.004" offset a reasonable simulation for out-of-control? If equipment is accurate to +/-0.002", then the programmed offset puts the actual placement offsets somewhere between 0.002" and 0.006".

In the current state of assembly technology, we talk about mils as if they were miles. It’s easy to forget that we are quite literally “splitting hairs” with this unit of measure. In printing, 0.002" of misregistration can easily be picked up in a bad setup, or by positional inaccuracies of the PWB. The group that performs our stencil scaling work reported the recent overall trend in PWBs is better positional accuracy, but they still occasionally see boards with 0.004" or 0.005" positional error in pad locations. The majority of errors they encounter are rotational; i.e., the X and Y axes do not meet at exactly 90°. In this case, the envelope of the board image is not truly rectangular; it’s more of a slight rhombus shape. No amount of X, Y or theta correction on the printer can compensate for this type of rotational error on the board image. The root cause of rotational error is in the axis setup of the photoplotter that generated the PWB images. It is completely out of the assembly engineer’s control.

So it’s relatively easy to pick up a few mils of slop in the printing process. Printers do a best-fit alignment of two solid images using three global fiducials. There is really no way for a stencil printer to make local compensations for PWB positional inaccuracies, but placement machines do have the capability to compensate – by using local fiducials. In this case, where the effect of PWB inaccuracy can be accommodated, the source of the slop is not typically associated with the PWB; it is often within the machine itself. Pick-and-place machines are electromechanical marvels. The rate at which they can cycle – pick a component, capture and analyze its image, adjust its position and rotation, and place it – absolutely amazes people outside our industry. But, they are still electromechanical in nature. Wear and tear can take a heavy toll on long-term performance. A regularly occurring 0.002" placement error can easily go undetected in a production environment; most component leads would not visibly overhang their pads with this offset. A 0.004" offset may be noticeable on gullwing leads, but could likely go undetected on chip components. An 0402 device would have to be placed 0.008" off center to begin overhanging the edge of its pad. All things considered, 0.004" seems a reasonable offset to test – not so close that machine error could put it back on center, but not so far that it immediately would be detected.

Another consideration regarding registration is the fact that we forced the 0.004" compound error on 25% of the components, which is likely more often than would typically occur in real production. Therefore, the overall defect levels may not be indicative of an actual assembly process’ output as it begins straying out of control. However, if we look at the 25% of components that were held to 0.002" in print and placement variation, we see very respectable defect levels: less than 100 ppm for no-clean pastes in both SnPb and Pb-free alloys (solder balls excluded).

Although I have read about increased tombstoning defect rates with Pb-free solders, we certainly did not see that trend in this experiment. With more than 100,000 0201 components placed in each paste type, tombstoning rates for the overall dataset were roughly 700 ppm for Pb-free and 1100 ppm for SnPb.

There are a number of interesting findings in the data, but if I had to select one, it would be that of the top four leading causes of defects, only one of them can be controlled by the assembler. And, as luck would have it, that cause happens to be the one that has the largest impact on process quality. This type of good fortune does not come often to process engineers, and it should be fully appreciated when it does. If we had found that the only way to decent yields was to run only resistors oriented at 90° in nitrogen, then we’d have something to complain about. But the fact that the best thing we can do to achieve high yields on 0201s is tune our printing and placement processes – well, that’s almost too easy!

It’s no secret that I am a big proponent of proactive process control. The experiment results provided me with more ammunition on my soapbox to preach about the long-term payback of small, upfront investments in maintenance and calibration. We crunched the data from many different angles, but it always showed the same result: Keep the process under control and the defects disappear.

A few final notes on this study: It was a substantial undertaking by a collaborative group of engineers and scientists at Jabil, Fuji, VI Technology and Alpha Metals who are due many thanks for their tireless efforts. This study was split into two phases. The current report reviews Phase 1. Phase 2 findings will be published in Spring 2008.

Chrys Shea is an R&D applications engineering manager at Cookson Electronics (cooksonelectronics.com); chrysshea@cooksonelectronics.com. Her column appears monthly.

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