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High-speed signal propagation obviates test points, driving a new solution.

Test and Inspection

In their search for increased data rates between devices, board designers are replacing externally clocked parallel busses with serialize/deserialize (SERDES) structures. These are characterized by gigabit per second transfer rates, differential A/C coupled point-to-point channels, and well-characterized transmission traces between devices. These structures also have low power consumption (1.1 mA per pin), immunity to common mode noise and low electromagnetic interference (EMI).

High speed signal propagation (HSSP), however, introduces a new set of ICT challenges onto the manufacturing floor. ICT relies on having good contact points between the device under test (DUT) and the ICT tester resources (Figure 1). However, in order to maintain the integrity of HSSP nets, test points are not permitted.

In the absence of test points on a trace, the test engineer has to consider the use of limited access solutions, such as boundary scan. Recently, the IEEE 1149.6 standard was released to enable boundary scan testing through AC-coupled differential structures. Some benchtop boundary-scan and ICT test vendors now are supporting this new standard on their systems.

While 1149.6 is an important tool, it is not a complete solution to the HSSP problem. Note it requires BSCAN compliance for devices on both ends of the high-speed channel. If there is an unpopulated connector or noncompliant device, then 1149.6 will not help. It’s still desirable to get traditional ICT probe access in these situations.

A recent advance in ICT probing is gaining popularity. Called bead probes, the idea is to unmask existing high-speed traces and apply a small smudge of paste to the exposed copper. During reflow, a sharp hemisphere of solder is formed, roughly 0.005" wide, 0.020" long and 0.002" to 0.003" high. It has negligible impact on the high-speed characteristics of the trace. A flat-faced probe in an ICT fixture can hit it reliably, thus recovering ICT access to these nets. Recent advances have extended the bead technique to include microvias. Figure 2 shows a photo of beads used on high-speed signals between a device and DIMM connector.

HSSP not only poses access challenges for ICT, it poses defect challenges too. Why? Maintaining the integrity of a high-speed channel means testing not only for defects on the signal pins (including both sides of a differential pair), but also on ground return pins. Traditionally, ICT has overlooked this side of the path, since defects on redundant ground returns could not be detected, and the effect of a missing ground was negligible to the overall performance of the board. For HSSP channels, however, a missing ground (perhaps an open on a connector) can result in increased BER, radiated EMI, and field unpredictability. A relatively new solution in the form of network parameter measurement effectively detects opens on power and ground pins on connectors. This capability enables coverage that could otherwise escape even functional test.

Bibliography

M. Doraiswamy and J. J. Grealish, “Implementation of Solder-Bead Probing in High Volume Manufacturing,” IEEE International Test Conference, October 2006.
K. P. Parker and Steve Hird, “Finding Power/Ground Defects on Connectors – A New Approach,” International Test Conference, October 2006.
IEEE Std. 1149.1-2001, “IEEE International Standard Test Access Port and Boundary-Scan Architecture," 2001.
IEEE Std. 1149.6-2003, “IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks,” 2003.
K. P. Parker, “A New Probing Technique for High-Speed/High-Density Printed Circuit Boards,” IEEE International Test Conference, October 2004.
K. P. Parker, “Bead Probes in Practice,” IEEE International Test Conference, November 2005.
K.P. Parker, “The Effects of Defects on High-Speed Boards,” IEEE International Test Conference, November 2005.