MANASSAS, VA – ZESTRON, is pleased to announce that Senior Application Engineer, Ravi Parthasarathy, will present a technical study, "Defluxing of Copper Pillar Bumped Flip Chips" at the International Microelectronics Assembly and Packaging Society’s (IMAPS) Device Packaging Conference on Tuesday, March 8th. His presentation is part of the Fan-Out, Wafer Level Packaging & Flip Chip Track Session TP2: WLP & Flip Chip: Process & Materials (2:00 – 5:30 pm)

In comparison to wire bonding technology, flip chip technology provides higher packaging density (more I/Os), higher performance (shorter possible leads, lower inductance), smaller device footprints and lower packaging profile. Copper Pillars are likely to become the most dominant type of flip chip interconnect in the coming years because they allow for pitches down to 40µm as well as improved electrical performance. However, post-solder flux residues can affect reliability and underfill, leading to delamination and voids. “Our study focuses on the impact of flux cleaning using straight de-ionized water and novel low-concentration aqueous cleaning agents on copper pillar bumped flip chips. The benchmark established in this study helped with Phase II study involving bump pitches lower than 15µm and denser packages. We are excited to present our findings at the IMAPS 19th Device Packing Conference” said Ravi Parthasarathy.

ZESTRON is a leading provider of cleaning solutions for the semiconductor industry focusing on advanced packaging including stacked copper pillar, FOWLP (2.3D/2.5D/3D) and and fCBGA packages. With ZESTRON’s cutting-edge technologies and experienced team of engineers, ZESTRON offers innovative and reliable cleaning processes for power electronics, advanced packaging, and wager bumping processes.

To learn more about ZESTRON’s capabilities within the Semiconductor industry, click here to download informational flyers: https://pages.zestron.com/semiconductor-flyers 

• Prev
• Next