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WASHINGTONNew orders for manufactured goods in June, up four of the last five months, rose 1.2% to $406 billion, the highest level in the 14 years U.S. Census Bureau has tracked the data.

Shipments, down two of the last three months,

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CAMBRIDGE, UK -- The number of companies offering Real Time Locating Systems has tripled in the past year. While in the past RTLS equipment has consisted of either very short range systems or complex, multiple antenna, multiple beam long-range RFID, new portability and affordability is sharply increasing its use. RTLS is now forecast to become a $2.71 billion business in 2016, according to a report from analysts IDTechEx.

RTLS are electronic systems that are intended to locate small electronic devices on people or things at any time. They are used in everything from hospitals to personal security to supply chains tracking.

SAN JOSE – SEMI (semi.org) has formed a working group of member company volunteers to provide expertise and guidance on intellectual property issues. Most of the activities are centered on education and government relations.

The group recently commissioned a best practices paper on IP protection. The paper,  Read more ...
NISKAYUNA, NY -- Binghamton University’s Integrated Electronics Engineering center (IEEC) and General Electric’s Global Research Center (GRC) have established an annual research symposium on National Trends in Small Scale Systems and Microelectronics Packaging. This year’s symposium will take place at the GE GRC facility in Niskayuna, NY, on Oct. 23-24.

It will offer information about promising new technologies and developments that are now impacting the electronics industry. Participants will receive overviews and research reports on a range of emerging technologies including: Nano Materials for Electronics, Flexible Electronics, NEMS/MEMS Developments, Optoelectronics, Sensors, Thermal Management, Sensor Packaging Integration, EcoElectronics - Lead Free Developments, BioElectronics, and Green Materials.

Approximately 150 participants, including development engineers and technical managers from major electronics companies and researchers from universities and government laboratories, will attend. Keynote presentations will provide an overview of recent developments in several areas vital to small scale systems and microelectronics packaging.

For the full program, visit:  wtsn.binghamton.edu/coned/EP06Main.htm
SINGAPORE — Marvell, a fables semiconductor company, broke ground this week on its new regional headquarters in Singapore. The 100,000 sq. m. facility will house  regional headquarters and include integrated design (IC) assembly and test operations, IC design, sales and technical support functions. The RHQ is expected to be completed in mid-2008.

Marvell currently employs 200 people in Singapore and plans to increase the number of employees to more than 500 within the next five years focusing on IC design and test and assembly engineering staff.

The company has operations throughout Asia including Malaysia, China, Japan, Taiwan and India.

Today, Singapore hosts 20 chip assembly and test plants, 14 wafer fabs and 40 IC design companies.
Tokyo and Santa Clara, CANEC Corp., NEC Electronics and NEC Electronics America today unveiled a new system-in-package (SiP) technology capable of stacking logic and gigabit-class memory in a single package to enable high-speed, high-definition image processing in mobile devices.

The technology, SMAFTI (SMArt connection with Feed-Through Interposer), features a 3-D chip connection whose approx. 60-micron gap and 50-micron-pitch microbump between the logic and memory devices can support transmissions up to 100 gigabits Gbps.

“The strong demand for digital video tv, digital video gaming and other digital video capabilities in portable consumer devices is driving the need for high-speed image processing that realizes crystal-clear resolutions,” said Takaaki Kuwata, general manager, Advanced Device Development Division, NEC Electronics. “SOC technologies present a disadvantage in terms of development cost and memory capacity, while conventional SiP products have larger package sizes due to thicker interposers, and have limitations in signal transfer speed, wire-bonding interconnections, and side-by-side chip placement. The new technology resolves these issues and enables engineers to effectively design and manufacture high-performance systems for mobile electronic devices.”

The technology leverages three key enabling technologies: a 50-micron-pitch microbump interconnection technology, a 15-micron-thick feed-through interposer (FTI) based on superconnect technology and a multichip assembly process.

The microbump interconnection realizes low power dissipation, a small form factor and high-speed interchip communication at more than 100 Gbps. Reduces the size of conventional pitch bumps and accommodates four times the number of bumps in the same area. Produces reliable high-speed data transfers.

Superconnect technology is used in chip fabrication and has a copper signal trace 15 microns wide and a polyimide layer 7 microns thick. Can convert a chip’s wiring pitch to 50 microns and fan out the pitch connection of an outer ball grid array to 500 microns. Routing of signals from a logic chip with a 50-micron pitch and memory connection points to universal substrate terminals can be simplified.

The multichip assembly process enhances existing wafer-based manufacturing processes typically used for SOCs. Memory chips are first mounted onto silicon wafers using wiring based on superconnect technology. Then the chips and wiring layer are molded by resin and the silicon wafer is removed. The BGA attachment process follows.

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