MINNEAPOLIS, Dec. 21 -- The second International Wafer-Level Packaging Congress will take place Nov. 3-4, in San Jose, conference organizers announced today. The event will explore cutting-edge semiconductor packaging, including chip scale, 3D, system-in-package, system-on-chip, system-on-package and wafer level.

Co-chair Dr. Ken Gilleo of ET-Trends LLC said in a press release that feedback from attendees "will allow us to expand on topics that are the most important and useful to attendees. The goal is to enable attendees to gain a great deal of practical information about wafer-level packaging that they can immediately apply to their work."

Exhibit space will be available, said conference sponsor SMTA, adding that IWLPC 2004 sold out.

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