IWLPC Program Finalized, Registration Opens
SAN JOSE, CA – The 10th Annual International Wafer-Level Packaging Conference will be held Nov. 5-7 at the DoubleTree by Hilton Hotel here.
On Nov. 5, four application-oriented tutorials on interposers, TSVs, wafer-level packaging, and choosing between technologies will be presented. Presenters include Rao Tummala, Ph.D., Georgia Institute of Technology, Luu Nguyen, Ph.D., Texas Instruments, John H. Lau, Ph.D., Industrial Technology Research Institute, and Herbert J. Neuhaus, Ph.D., TechLead Corp.
The conference, on Nov. 6 and 7, includes three tracks of technical paper presentations, covering wafer level packaging, 3-D (stacked) packaging, and MEMS packaging.
The technical committee added two technical sessions on 2.5/3D integration, and a session for metrology and test was created.
Paul Wesling, a CPMT Society Distinguished Lecturer, is scheduled to keynote a history of device technology development and innovation in his presentation "The Origins of Silicon Valley: Why and How It Happened Here.”
More than 50 exhibitors are scheduled, with a few booths remaining.
Registration is now open, and early bird conference pricing is in effect until Oct. 4.
For more information, visit http://www.iwlpc.com.
