LEUVEN, BELGIUM – IMEC and the Microsystems Packaging Research Center at the Georgia Institute of Technology invite interested parties to join a research program on next-generation flip-chip and substrate technology. The program addresses key IC-to-package to board packaging interconnect issues for 32 nm ICs and beyond.
 
IMEC and Georgia Tech will explore, develop and invent solutions to interconnect high-density ICs with tight I/O pitches (20-40 µm peripheral) to low-cost packages and PCBs. The program targets novel packaging approaches to reduce the mechanical stress on the IC after packaging and assembly.
 
The program plans to provide solutions for the four major barriers to next-generation flip-chip packaging of scaled ICs and ultra-low-k dielectric ICs. Its aim is to explore and develop organic package interposer substrates that minimize stress at die and package level and enhance the wiring density, the fine I/O pitch routing capability and the high-frequency signal performance of substrates; a new generation of fine-pitch flip-chip UBM (under-bump metallization) and barrier metallization that meet the electromigration and thermo-mechanical reliability targets of flip-chip scaling; novel solder and non-solder interconnect approaches, including advanced underfill materials and processes to meet future current density, geometry and reliability requirements; thermo-mechanical modeling, design and verification for improved reliability.
 
The two-year program is open for the entire supply chain. The program plans to bring together 20 to 30 expert researchers from industry and academia worldwide.

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