HALF MOON BAY, CA -- Attendees on the second day of the SEMI Strategic Materials conference learned how Japanese materials suppliers joined together to cut costs, and were given an optimistic outlook on the convergence of front-end and back-end processes in chip making.

Yoshifumi Kawamoto, director general manager, R&D department, CASMAT, outlined the formation of the R&D consortium established in 2003 by Japanese materials suppliers. Member companies include JSR, Sumitomo Chemical, Sekisui Chemical, Tokyo Ohka Kogyo, Nitto Denko, Hitachi Chemical, Toray Industries and others.

The consortium operates a 1,300 sq. meter clean room equipped with 300mm wafer technology for 65-nm back-end of line (BOEL) processing.

The motivation for forming CASMAT was to give materials suppliers access to the expensive equipment necessary to develop integrated solutions, according to Kawamoto. “Materials suppliers need equipment to develop integrated solutions but the cost of the equipment is too high,” he said.

Under the consortium model, member companies develop new materials and CASMAT undertakes the evaluation of the materials. This accelerates development time and allows device makers to get their products into production earlier.

CASMAT is focused on four key areas: low-k materials, CMP slurries and pads for copper/low k interconnects, buffer coat organic material, and back grind tape and dicing tape for the assembly process.

Kawamoto noted that to continue its success CASMAT needs to undertake further collaborations with other consortia, device makers and equipment suppliers.

Arthur Zafiropoulo, chairman and CEO of Ultratech, said that the border between wafer fabrication and device packaging was getting blurred because leading-edge flip chip, wafer level package and post-passivation technologies increasingly use front-end fab processes.

Advanced packaging will grow at a 20% CAGR from 2005 to 2008 and flip-chip technology will enable next generation portable and high performance electronic products, according to Zafiropoulo.

Currently 10% of all wafers are bumped, growing to an estimated 35% by 2010. The cost of bumping dropped below the cost of wire bonding in 2003, but wire bonding will never go away completely, said the Ultratech CEO.

A typical 300mm bump line producing 10K wafers per month would cost around $30 million, and uses many of the same processes found in the front-end, including lithography, sputtering, strip and etch. “Now the back-end in flip chip seems just like the front-end, but it’s a lot cheaper,” said Zafiropoulo. Further, he believes these lower cost bumping fabs will begin to sprout up in China, outpacing local investments in wafer fabs which can cost up to $3 billion.

On Jan. 12, the first day of the confrerence, speakers asserted new semiconductor materials will be the key to continued scaling of devices in line with Moore’s Law, but industry-wide collaboration will be essential to reduce development costs.

“New materials will continue to fuel innovation, I don’t think there is any doubt about that,” said keynote speaker Thomas N. Theis, director of physical sciences for IBM’s T.J. Watson Research Center. “But this kind of innovation can be very expensive and that gets us to collaboration and partnerships.”

Technical issues such as power dissipation and device variability were the roadblocks to improving performance through further scaling, according to Theis. “We are going to continue to shrink the devices, but we are going to have to do it with new materials and new device structures otherwise the shrink will not work,” he said.

Theis also raised the question of a possible replacement for silicon. While he believes silicon transistors will be around for another 10 years at least, he noted that there are efforts by labs, universities and companies to search for a new type of field effect transistor. “The ultimate FET may not contain silicon,” he said.

Jerry Ermentrout, general manager of the Electronics Division of Air Products, said that despite the high rate of change in the semiconductor industry materials have typically had relatively long life times. “That clearly is changing,” he said. Instead of spanning six or more technology nodes, materials are now applicable across only two or three nodes.

Ermentrout spoke out in favor of pre-competitive collaboration in the materials industry to close the R&D funding gap identified in a recent SEMI white paper. Many companies were doing redundant work in order to create a competitive advantage. “We have to do a better job of spending the R&D dollars that we are spending,” he said. “An increasing amount of collaboration could help us close the current funding gap.”

However, he warned that a major obstacle in getting companies to work together was intellectual property (IP). “What gets in the way too often is the IP and how to use it," he said.

Speakers also highlighted a trend for semiconductor companies to hire more materials scientists and physical chemists and fewer electrical engineers, signaling the importance of materials in future technology developments.

While most of the industry collaborations thus far have been in the wafer processing sector, some speakers called for more co-operation in assembly and test as well. David Bennett, director of strategic equipment technologies at AMD, noted that the cost of testing and packaging devices was approaching the cost of the wafer processing, providing an incentive for technology partnerships in the back-end.

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