Edina, MN --The SMTA is seeking papers for its third annual International Wafer-Level Packaging Conference and Exhibition. The event will take place on Nov. 2-3 in San Jose, CA, and will track IC packaging and test technologies with emphasis on 3-D stacked packaging.

Submit 200-word abstracts by e-mail to Melissa Serres (melissa@smta.org) by April 1. 

Dr. Ken Gilleo, ET-Trends LLC, Circuits Assembly columnist and SMTA VP of Technical Programs, and Terry Thompson of Chip Scale Review will co-chair the technical program.
 

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