Not everyone is. That’s a mistake.

It hit me while walking through IPC Apex Expo in February. Talking with various colleagues, the famous quote from A Tale of Two Cities kept repeating in my head: “It was the best of times, it was the worst of times.”

At every industry meeting I have been to in recent months, the mood has been quite bullish, reflecting the best of times. The HKPCA Expo in Shenzhen was well-attended, and money was being spent – lots of it! Ditto for Apex, where attendance appeared brisk and North American companies were in a buying mood. Discussions revolved around adding capacity, further incorporating higher technology capability, and exciting new customer relationships – all of which overshadowed the news that tariffs and trade restrictions could be in the offing.

A primer on the steps for building advanced PCBs.

To get more functionality out of boards but within the same or reduced board sizes or areas, OEMs are increasing the density of the product by means of high density interconnect (HDI) boards, which are PCBs with multiple layers vertically connected with blind or buried vias.

HDI PCBs use high-performance thin materials, and have fine copper lines and microvias. While various methods are available, some patented, some not, we use what’s known as Every Layer Interconnect (ELIC) technology, which produces very thin flexible PCBs with high functional density per unit area. Advanced HDI PCBs make use of multiple layers of copper-filled stacked in-pad microvias that enable interconnections with even greater complexity.

President Donald Trump issued an executive  order in March that introduced an often-threatened but rarely used measure to the world economic picture: tariffs.

Trump’s edict, which as of this writing was due to go into effect on Mar. 23, places onerous taxes on imports of steel and aluminum – 25% and 10%, respectively. The moves, the president said, were to reset trade imbalances and protect domestic metal producers, which have been decimated over the past two decades.

Or have they? The adjusted domestic steel production year-to-date through Mar. 10 was 17.2 million net tons, at a capability utilization rate of 74%. That is down 0.2% from the 17,221,000 net tons during the same period last year, when the capability utilization rate was 74.6%.
By comparison, total and finished steel imports over the same period were a combined 7.6 million NT net tons. The estimated finished steel import market share is 25% year-to-date.

One approach: Aperture designs that reduce paste volume from the inside wall.

While the primary theme of this column over the past few years has been miniaturization’s impact on stencil printing, standard SMT process challenges are alive and well. In many applications, where average device dimensions are large compared to the latest package footprints, reducing traditional defects is still a battle. One such frustration: mid-chip solder balls. To understand how to correct this well-known defect, one must appreciate the origin.

Mid-chip solder balls are most often observed with passive devices, specifically, resistors and capacitors. Since these chips have terminations on each end, solder paste material is deposited on two corresponding pads on the board; an open space of solder mask-defined PCB lies between them.