Routing flash has EMI implications. Don’t rush.

Memory comes in different types, and one key distinction is whether the memory remembers anything once the system is shut down. Nonvolatile memory stays around for the next session, while volatile memory lives up to its name and melts away between uses.

A little history with flash memory - used for storing software rather than data. Flash memory is the first kind. Your data are saved for posterity. Time was, the physical manifestation of flash memory was the electrically erasable programmable read-only memory (EEPROM). These chips were typically housed in 20-pin DIP (dual in-line package) formats and could be plugged into sockets for programming. Some versions, known as PROMs (programmable read-only memory), could be programmed only once.

When I worked in telecom, memory devices came in tubes, and the registers would be cleared, “all zeros.” The production line had a gang programmer, but my lab equipment could flash only one at a time. Naturally, this work was done at a static-safe desk, with an ESD strap secured around my wrist to prevent damage to the devices.

Before I could start, an engineer had to verify that the programming was up to date and suitable for the intended use. These checkpoints and logbooks were essential to meeting customer requirements, which had been shaped by past failures. To track the programmed revisions, we handwrote on sticky labels the dash-number revision of the data loaded onto each device. We’re talking about the mid- to late 1980s here.

Modern form factors and use cases for flash memory. Over the years, the DIP package gave way to surface mount options as well as more portable use-cases. We have SD card readers that mount along the edge of the printed circuit board with access to the outside world. This makes it easy to transfer data by plugging into another SD card reader. You’d normally see about eight signal pins and several chassis mounts for mechanical stability.

Figure 1. A cage for a micro-SD card showing the contact points. The signals are typically routed to a microcontroller or SoC just as for any kind of memory. (Credit: Amphenol)

Another form factor for external NAND flash memory is the USB dongle (Figure 2). However, it’s unlikely that we’d be tasked with creating the PCB for one of those, as countless manufacturers are already producing them. They will put your logo on the outside and call it a day. There are different USB types, but they’ll typically use the good old USB-A connector.

Figure 2. Who doesn’t have a fist full of promotional USB dongles? (Credit: Author)

If you are going to create a dongle, it will most likely use the USB 3.1 type-C connector. It will probably be somewhere between 64Gb and a terabyte of storage. The multiple superspeed lanes are useful in transferring that volume of data as a video stream or similar use case. These high-performance dongles are a step above the basic ones typically handed out at trade shows.

Solid state memory instead of a disk drive using PCIe standards. When it comes to more deeply embedded flash memory, solid-state drives (SSDs) have largely replaced traditional disk drives in portable devices. Those SATA architectural conventions are still in play, while solid state drives typically use some version of the PCIe standards.

The PCIe standard is versatile, offering swappable lanes and multiple configurations. Over the years, PCIe has grown along with the computer industry by adding lanes and increasing data rates (Figure 3). The PCIe special interest group supports other types of peripherals as well. Mini card and half mini card versions of PCIe were used as WiFi cards before Wifi was incorporated into laptops.

Figure 3. The PCI bus I/O bandwidth roughly doubles over any three-year period. A motherboard would have two connector slots minimum, one for graphics and another for memory. Both would be sensitive to location with respect to the SoC. (Credit: PCI SIG)

Implementing flash memory on a PCB. Implementing, in this case, refers to bringing the circuit onto the motherboard, also known as a main logic board or MLB. PCB-mounted flash memory comes in various packages, including old-school TSOP and the fresher BGA versions. What these packages seem to have in common is an abundance of no-connect pins.

A few years after releasing the 48-pin TSOP package (Figure 4), the 63-pin BGA was added to the lineup. Both packages utilize the same two stacked dies, providing a total of 8 GB of memory. The pin pitch is a generous 0.8mm, which permits normal plated through-hole vias. The silicon is large, but that is normal for memory devices.

Figure 4. A surface-mount flash memory device. Out of 48 pins, 25 are floating. There are 8 I/O pins, a similar number of control lines (collectively known as “command interface logic”) to enable the usual functions and a few VCC and VSS pins to power the two memory chips stacked inside the package. (Credit: SkyHigh Memory)

Why memory is normally in a separate package. The fabrication process for memory ICs involves much larger feature sizes compared to the fine geometry used for processor gates. A memory cache will likely be right on the processor, but it’s kept to a minimum. When it comes to mobile/wearable applications, the RAM is often stacked on top of the SoC, so the flash memory is often the only one that concerns us as PCB designers.

That was not the case for the Xbox. That main logic card had more DDR than I had ever seen on one board. I thought eight was enough. In any case, Microsoft had a way to make sure I didn’t touch the memory. They had many scripts, and one turned traces into equivalent shapes that were locked down.

Routing flash memory involves EMI considerations, so the circuit design can be adjusted freely until the first copper etching. If that initial iteration works, you’re stuck with it, so don’t rush these things.

Extending signal integrity to the control lines and the data bus. The command interface logic I mentioned in Figure 3 isn’t controlled impedance, but that doesn’t mean that we can route those traces over voids in the reference planes. Every signal should route within a Faraday cage. The main difference is that line width and space constraints will permit denser routing of the non-controlled impedance traces. Our concern isn’t so much about impedance as it is electromagnetic interference (EMI) within the system as well as outside the box (Figure 5).

Figure 5. This ball map includes several outlying pins that do nothing more than hold the component in place. The vendor can use an IC with smaller dimensions and omit the outer rows. That reduces the package size to near the length and width of the 48 central pins. (Credit: SkyHigh Memory)

Naturally, the particulars of the device will drive the technology. On-board read/write protocols for flash memory include I2C, SPI and EMMC. Each has its interrelationships and ensuing design rules. While some tolerance for length matching may exist, system engineers often prefer to retain as much margin as possible.

How much length-matching is enough? If all memory lines can be routed to the same length, there’s no debate – it’s ideal. I would prefer to find the longest line and subtract 90% of the available skew and route the clock to that length. The long tentpole would be as long as the clock plus the positive tolerance. Shorter traces are then lengthened just enough to meet the minimum deviation, leaving a 10% cushion.

The clock is just long enough to solve for the longest line. From there, the short traces are meandered to meet the threshold between too short and just enough compared to the clock. That would be most efficient in terms of effort and overall trace length, which should minimize radiation at the cost of using up the available margin.

The other school of thought is to match every line as closely as possible. Stretching all the lines, including the clock, to equal the longest one will maximize the margin. In practice, we’re likely to fall somewhere between those two limits.

It seems like the fewer lines there are, the more the length matching matters. You should already know how to make the concerned engineers comfortable. Knowing the specs and the personalities involved will help you do this in a FLASH.

John Burkhert, Jr. is a principle PCB designer in retirement. For the past several years, he has been sharing what he has learned for the sake of helping fresh and ambitious PCB designers. The knowledge is passed along through stories and lessons learned from three decades of design, including the most basic one-layer board up to the high-reliability rigid-flex HDI designs for aerospace and military applications. His well-earned free time is spent on a bike, or with a mic doing a karaoke jam.

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