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The Creation and Building of a Pb-Free Product
A case study in designing and building Pb-free 128Mb USB memory modules.
Over the past five years, Speedline Technologies has actively worked with numerous customers on Pb-free process implementation, both in process equipment requirements (our primary business) and process development. Process development projects - internal and with several major soldering material suppliers and academic institutions - are ongoing. In late 2004 we decided to design and build a functioning Pb-free product. Among our reasons: to gain additional understanding of Pb-free product design and manufacturing issues; to collect meaningful data during the build to identify defects that can be expected; to have product to give customers during trade shows or other events to demonstrate our Pb-free process expertise. We chose to build a 128Mb USB memory module.
This case study of our experience includes board design, stencil design, Pb-free solder paste selection, support tooling design, printing process development, reflow oven profile creation, quality data, defect detection and other observations.
With several Pb-free process projects finished and several more planned, we concluded we had done virtually everything in Pb-free process development short of actually building a working Pb-free product. What else could we do to better understand all the Pb-free process issues? We conceived the idea to build a working Pb-free product. After considering a number of product ideas the USB memory module seemed to best satisfy our requirements of budget, complexity, marketing (a tradeshow "giveaway") and, most important, education. The 128Mb size module is usable and fit our budget.
The first step for our memory module was to create a circuit design. We built a prototype (breadboard) using the schematic. Once the prototype was built and tested we immediately started designing the circuit board. We had the required mechanical size of the board since we had selected the plastic case for our 128Mb USB memory module. We acquired the specification for all components and supplied them along with the required board size to the designer (Table 1).
Next, we built two models using the PCBs we designed and the components from our bill of materials. Fortunately, the two models worked the first time with no component or circuit changes required. We then started purchasing all the components to build 1,100 units. Before ordering boards, we had to design the working panel or palette that would contain multiple individual memory module circuits. The individual circuits were small (0.56 x 1.28") so we elected to build panels containing several individual circuits. After considering several designs, we decided on a 5.25 x 7.5" panel that contained 14 individual memory module circuits (Figure 1). The board is four layers and 0.032" thick. We designed the panel with routed and scored breakaway sides so individual circuits could be separated from the panel without any tools. We used a NiAu finish to ensure a flat surface for the pads.
Stencil design. Stencil design is a critical factor affecting stencil printing process performance. Table 2 shows stencil opening dimensions and their corresponding area ratios. The dimensions for chip components (resistors and capacitors) were reduced by 0.001" from their nominal pad dimensions. The aperture reduction was carried out to reduce the occurrence of solder balls and solder bridging. However, devices U1 (QFP) and U2 (TSOP) were treated differently. If the stencil had been designed with openings matching to the pad dimensions, the area ratio for both the components would have been 0.66 (U1) and 0.63 (U2). These area ratios are close to violating the area ratio criteria (AR > 0.6). Therefore, the stencil openings for U1 and U2 devices were increased by 0.001".
Solder paste selection. Pb-free pastes from different manufacturers were used in the initial evaluation. It is important to select a paste that will satisfy all requirements for that particular application. The performance of the pastes was evaluated on print and reflow (air and nitrogen atmosphere) quality. All Pb-free pastes exhibited acceptable print performance. With respect to reflow, paste from one manufacturer had exceptional reflow quality in both air and nitrogen atmospheres. Pb-free joints reflowed in air were shiny and had complete pad coverage. The paste that showed exceptional reflow quality in air was selected for our assembly builds.
Assembly Process
The following sections describe the assembly process steps involved in manufacturing Pb-free memory modules.
Solder paste printing. An MPM UP3000 stencil printer was used for printing. Print optimization was carried out to select the printing parameters for printing process. Optimization helps determine the parameters, which in turn provide a consistent and higher volume of paste for assembly. The following print parameters were used for the printing of Pb-free memory stick board:
Print pressure: 15 lbs. (1.5 lbs./in.)
Print speed: 2.0 in./sec
Separation speed: 0.05 in./sec over 0.1 in (slow snap-off)
Wipe frequency: 5
The printer was set to wipe the stencil every five boards to prevent the occurrence of bridging in QFPs and TSOPs, because apertures for these components were oversized.
It is important to adequately support the board during the printing process. The first side of the board was supported with standard blocks. The support area was equivalent to the board footprint. Because components were already assembled on the underside of the board when the second side was printed, we designed and built a custom tool (Figure 2) that supported the board while providing clearance for the bottom-side components. Other methods for second-side support include magnetic support pins, selectively activated support pin tools and GelFlex1 tooling. A dedicated work holder provided the best support during the print operation but has higher cost and less flexibility.
Inspection. A 2-D inspection system within the stencil printer was used to inspect paste coverage on selected components within the board. A GSI 8200 laser Profilometer (with a 2X scanner) measured the volume of solder paste deposited on individual pads. A Gauge R & R study was performed to verify its capability and the P/T ratio showed the inspection system to be capable of measuring these solder deposits.
Component placement. A fully automatic dual-head pick-and-place machine (Assembléon ACM Micro) was used for placement. The placement speed and pressure were based on recommendations provided by the equipment and component manufacturers.
Reflow process. A Speedline Electrovert OmniExcel 10 oven was used for reflow. Figure 3 shows the reflow profile used. Boards were reflowed at a peak temperature of 238°C and a time at liquidus (TAL) close to 45 sec.
Print Inspection Results
Stencil printing can reportedly cause more than 50% of assembly defects.2 To reduce the occurrence of these defects, continuous process monitoring of the stencil printing operation is necessary. This is achieved by using both internal (2-D) and external (3-D) AOI systems. The 2-D inspection system measures how much of the pad is covered by solder paste while the 3-D AOI measures the volume of each solder paste deposit by means of laser triangulation.
To monitor the performance of the stencil printing process, specification limits were defined. The performance of the print process is verified to fall within the specification limits before the board is permitted to proceed for the next assembly step (pick-and-place). If a board fails automated inspection criteria, the board is rejected from the assembly line, thereby providing an opportunity to identify the source of error and repair the defect.
Data Analysis
2-D inspection. The 2-D inspection system was programmed to measure the pad coverage for each board at six different modules within the board. Figure 4 shows pad coverage for the first-side build. Nearly all boards inspected exhibited solder paste pad coverage between 90 and 100% (except board no. 22). The pad coverage in board no. 22 was 81%, which is acceptable because pad coverage is greater than the lower acceptance limit (LSL of 80%). The pad coverage data show that the established stencil printing process is very consistent and the process is in tight control.
Figure 5 shows pad coverage for the second-side build. Similarly to the first-side, the 2-D inspection system was programmed to measure pad coverage for each board at six different modules within the board. For the majority of the boards the solder paste pad coverage falls within the specified limits of 80 and 100%. However, the data show increased variations in pad coverage. It is believed that this is due to the board warpage resulting from the first reflow. As the board warps, images acquired by the inspection system will drift out of optimal focus. This will in turn produce less accurate measurements. The pad coverage data show that the established stencil printing process is and the process is in control.
3-D inspection. A 3-D inspection system was used to collect volumetric measurements. To evaluate the performance of the solder paste printing operation, process capability indexes (Cp and Cpk) were calculated. The process capability index shows how close a process is running to its specification limits, relative to its natural variability. The larger the index, the less likely the process will fall outside the specification limits. The process capability indexes were calculated using a specification of 0.005" (stencil thickness) +/-0.002" for height measurements and +/-40% of target volume for volume measurements.
Figure 6 shows the distribution of height and volumes for the memory (U2, TSOP) on module 12 in first-side assembly. The Cp and Cpk indexes for both height and volume show that the stencil printing process is within control and performs within the specified limits. Similar results were observed for the other modules present on the board. 3-D data were not collected for second-side assembly because board warpage was too large to permit an acceptable measurement. For the 3-D inspection technique used in this work, boards should be nearly flat and have traces or reference area close to the measured solder deposits.
Defects. A first-pass yield of 95.49% was achieved for the Pb-free memory stick assembly build. A total of 1064 modules (78 boards) were built, of which 48 modules were found to be defective. To better understand the source of defects, each module was visually inspected and tested. Defects were classified into nine categories (Figure 7). The majority of defects were QFP polarity defects, in which the polarity of the placed QFPs did not match the pad configuration.
Additional effort focused on identifying the source of each defect. Figure 8 shows the distribution of defects by source of defects. The major contributor of defects in the entire assembly process was placement. Identifying defect sources provided valuable information to fine-tune the process at a later stage.
Design Changes
After evaluating the quality and yield data, we determined the defect count could be reduced by making three changes to the board design (Figure 9). The first change was to the spacing for the USB connector's tabs (legs). The spacing and hole size recommended by the connector supplier proved too tight to insert the connectors using our placement equipment. As a result, we had to place them manually. However, even manual assembly proved to be difficult and the excess force applied at the time of connector insertion caused several defects. We experimented with alternative spacings and found one that allowed us to virtually "drop in" the USB connector. We can now use our placement machine to place the USB connector.
The second change was for one of the four pins on the USB connector. One pin had a soldermask-defined pad on a large ground plane. Although the soldering of this pin was acceptable, it was not ideal. The soldermask-defined pad took longer to reach reflow temperature than the independent, copper-defined pads. We changed the design to make the pad for this connector pin a copper-defined pad connected to the ground plane with an etched trace.
The final design change was to correct the pad size for one of the capacitors. We were able to reliably assemble this capacitor but the pad size was too small for optimum quality. We changed it to a larger pad size. All the design changes have been incorporated for the next build.
Lessons Learned
Many issues we experienced in building our 128Mb memory modules are the same we have heard from customers and seen during factory floor support. For example: one problem initially experienced during the model build was tombstoning of a few of the resistors and capacitors. We minimized this by optimizing our printing process to ensure equal solder paste volume on each printed pad and to verify accurate component placement.
Another problem: warpage of the board during first-side build. At 0.032" our boards are relatively thin and they experienced a degree of warpage from the Pb-free profile heat during first-side build. For the most part, we were able to compensate for the warpage by making slight process changes. In the future we will use the centerboard support feature of our reflow soldering oven. The centerboard support is designed to support the board during its entire travel through the reflow solder oven and eliminate warpage.
Another problem was the design issue of soldermask-defined pads associated when one of the two component pads has a large ground plane while the other is a standalone, copper-defined pad. Such design causes a dramatic imbalance in the reflow soldering times. In our design, this problem only caused some non-optimal soldering. At customer sites we have seen this problem cause a high incidence of component tombstoning. Circuit board pads for chips and discrete components (primarily resistors and capacitors) must be of the same size and fabrication technique. If one pad is a standalone copper-defined pad of a particular size, the other pad must be the same.
One observation was the use of the component supplier's recommended pad layout. In almost all cases, using the recommended layout for a particular component is good practice. We experienced a case where the supplier-recommended pad did not provide the optimum layout. We recommend that when using electro-mechanical components such as connectors that have through-hole pins or tabs, test the pad layout prior to volume build of boards. As discussed, we were unable to automatically insert the USB connector. We had to manually insert it, which caused some defects.
Conclusions
Building our own working Pb-free product was an excellent learning experience as well as a good practice drill. We verified much of what we had learned over the past few years and gained some practical experience. We feel our research and customer support experience allowed us to achieve a relatively high first-pass yield for a first-time Pb-free product build. The process window has narrowed and the attention to process details must be increased when using Pb-free soldering materials. A thorough understanding of each component's maximum and rate of rise temperature tolerance is vital to ensure components are not damaged.
The key to a successful high-yeild Pb-free manufacturing process is the same as with all process development and implementation work: good engineers doing good engineering work using formal studies and experimentation to understand and quantify all factors of the manufacturing process. Remember: Pb-free material is not merely a materials change, it is a technology change.
References
Bhosale, et al, "A Cost Effective Solution for Supporting Populated Circuit Boards during the Solder Paste Print Operation," IPC Apex Proceedings, February 2003.
Clouthier, "SMT Printing Process for Fine Pitch and Ultrafine Pitch," Surface Mount International Conference Proceedings, August 1997.
The authors, Srinivasa Aravamudhan, Joe Belmonte, Anand Bhosale, Alden Johnson, Karl Moore and Dr. Gerald Pham-Van-Diep, wrote this article while at Speedline Technologies (speedlinetech.com); jbelmonte@speedlinetech.com.
