A new substrate demonstrates superior results under accelerated thermal cycle test and finite element modeling.

Trends toward miniaturization and higher functionality will drive greater demand for interconnection density at IC, package and board levels. The semiconductor industry has now reached a historic transition: nano chips with less than 100 nm features with several hundred million transistors that require I/Os in excess of 5,000 and power in excess of 100 W, providing computing speed in terabits per second. These requirements, together with digital and wireless systems around 20 GHz in the future, require new paradigms both in IC packaging and systems packaging.¹ The routing of future ICs with 10,000+ I/Os requires ultra fine feature sizes of about 10 µm lines/space widths and 20 to 30 µm pad diameters. Targets for leading-edge substrates are:

1. Wiring density of above 5,000 cm/cm² to support I/O density of 10,000/cm².
2. Signal integrity to support five to 10 Gbps data rates requiring ultra-low-loss dielectric materials with loss tangent ~0.001.
3. Power integrity to support >100 W power with <50mV DI noise achieved by means of embedded decoupling capacitors in the package.² Fine-pitch short interconnections with the least electrical parasitics are critical for signal and power integrity.

Two major components of high-density packaging are multiple layers of conducting copper patterns with interlayer dielectrics on a board and multiple ICs flip-chipped on the top layer. A range of passives, waveguides, and other RF and optoelectronic components will be buried within the dielectric layers, shown conceptually in Figure 1. The interleaved copper and dielectric layers also support the high-density interconnects for power and signal requirements. The board material should therefore meet certain electrical, thermomechanical reliability, fine-line multilayer processing and cost requirements. Current substrates impose several fundamental barriers in meeting the reliability and stringent processability requirements of these convergent multifunctional microminiaturized systems. The fundamental barriers for today’s substrate materials and the need for novel substrate materials are discussed here in the context of increased functionality, wiring densities and reduced feature sizes.

The 2003 ITRS roadmap called for organic substrates with less than 100 µm area-array pitch in the package or board by 2010.³ IC assembly reliability is affected by thermomechanical strains/stresses induced in the package due to differences in thermal expansion coefficients among different components in the assembly under various thermal excursions. These thermomechanical stresses result in low-cycle fatigue failure of solder joints, delamination of the solder bumps, or cracking of the buildup layers, leading to assembly failure. A silicon die has a CTE in the range of 2 to 3 ppm/°C, while the conventional FR-4 substrate has a CTE in the range of 18 to 20 ppm/°C. By employing underfills, thermal strains at the solder bumps can be effectively reduced to improve the solder bump reliability. Nevertheless, underfill dispensing becomes more complicated as gaps narrow and shorten, as interconnections with larger dies require. Underfill is also known to cause the package to deform, leading to large peeling stresses at the die underfill and die-solder interfaces that significantly impact packaging reliability.

The effect of board material on solder strains was studied using a 2-D finite element model. FR-4 without underfill experiences a high equivalent plastic strain in solder balls when cooled from reflow temperature to room temperature, an order of magnitude higher compared to silicon CTE-matched substrates. Figure 2 shows that the plastic strain in the solder is about 0.008 for 2 ppm/°C C-SiC boards and 0.091 for the FR-4 board. These results indicate that the flip-chip assemblies on FR-4 base substrates without underfill are highly susceptible to solder fatigue failure compared to the CTE-matched base substrates, as would be expected. Therefore, a compelling need exists to develop cost-effective board materials with a CTE close to that of silicon for reliable assembly without the need for underfill.

High-Density Routing and Dielectric Reliability

Future systems boards will need four to eight layers of five to 10 µm wiring. The stringent need to process multiple layers of thin films with via sizes of 10 µm and capture pads less than 20 µm requires layer-to-layer misregistration of less than 10 µm over a 300 mm substrate. This in turn requires warpage control of five to 10 µm per inch for a 0.65 mm thick substrate⁴. Substrate warpage also becomes critical for the emerging 3-D packaging technologies such as PoP (package-on-package). Today’s board materials have fundamental limitations in terms of warpage, interconnection stresses and dimensional stability considerations as indicated in Figure 1.

Low CTE boards escalate dielectric stresses to the point that dielectric cracking and delamination become critical concerns. Figure 3 shows the role of substrate and dielectric properties on the dielectric reliability using the multilayered substrate. The maximum dielectric stresses in the buildup layer are sensitive to CTE mismatch and dielectric modulus, but not a strong function of the number of buildup layers, as seen from the figure. However, our results show that a thick epoxy dielectric layer might lead to cracking, while a thinner buildup layer does not lead to any failures on low CTE substrates. Suitable dielectric material properties and buildup layer thickness are critical to ensure their reliability on low CTE boards.

Cu-low k integrity. Cu-low k structural integrity of on-chip interconnects is another major reliability concern for high-density flip-chip packages. Interfacial delamination is common in low-k or ultra low-k on-chip interconnects after IC assembly because of the large deformation and stresses generated by thermal mismatch between the silicon die and the substrate. In the wafer backend process, the crack driving force results from thin film residual stresses within each layer and thermal mismatch stresses within the low-k stacks. During package and IC assembly, in addition to the residual and thermal mismatch stresses within the Cu-low k stack, the global thermal mismatch between the package and IC exerts considerable external loads on the on-chip Cu-low-k structures. Compared with oxide, the low-k dielectric is softer, expands more and adheres weakly to other materials. Cu-low k is known to have a fracture toughness of 1 J/m² compared to oxides and oxynitrides (8-16 J/m²) and Cu-epoxy (25 J/m²). The low adhesion strength of the passivation/low-k dielectric interface makes it prone to delamination. While this indicates that interfacial delamination is not a critical issue for standalone die, the problem is commonly observed in Cu-low-k interconnects after the die assembly. Eliminating the CTE mismatch between the package and IC can minimize Cu-low k reliability problems.

Figure 4 shows the generalized plane deformation finite element model for a 100 µm flip-chip assembly of a 20 x 20 mm chip on a low CTE board. Figure 5 show various effects of underfilling and board material on die stresses. While underfilling increases die stresses in silicon die, they are significantly lower with C-SiC substrates without underfill. These results demonstrate the significance of high modulus low-CTE material as a potential board material for next-generation packages, particularly ones with inherently weak Cu-low k ICs. The CTE-matched substrate assembly without underfill reduces die and interconnection stresses by an order of magnitude compared to traditional FR-4 with underfill, and also makes the stresses insensitive to the interconnect pitch and the chip/PWB thickness ratio, making it attractive for finer pitch packaging and die thinning.

Advanced Organic Substrates

Novel laminate materials with advanced fillers address some limitations of existing substrate materials. Low-cost epoxy-based laminates with a CTE of eight to 12 ppm/°C are available; these laminates also have 20 to 30% higher modulus than FR-4/BT⁵. EIT’s HyperBGA is a 150 µm pitch flip-chip attachable package with thin low-CTE metal core, 50 µm thick PTFE-based dielectrics, 50 µm through-vias with 28 µm lines and 33 µm spaces⁶. EIT’s Hyper-Z package has the same CTE with a low-loss organic substrate, for packaging 150 µm pitch ICs. DuPont's nonwoven aramid reinforced laminates (Thermount) have tunable in-plane CTEs that reduce the mismatch between the semiconductor and laminate substrate⁷. A similar approach was reported by AT&S⁸. This results in reduced strain on solder joints during thermal cycling, creating a higher reliability package. These materials have also shown to be laser drillable. Organic chip carriers developed in Japan and Asia use BT resin laminates and have demonstrated 225 to 250 µm pitch flip-chip capability. Leading microvia substrate manufacturers in Japan and Korea such as Ibiden, CMK, Mektron, Samsung and others are currently manufacturing substrates with 20 to 25 µm lines and spaces and 40 µm microvias⁹. ThermalWorks recently developed a hybrid laminate consisting of a high stiffness, high thermal conductivity, low CTE, carbon cloth polymer core with outerlayers of FR-4 lay-ups.

Recently, thin core or coreless substrate technology is emerging as the choice for the most demanding system applications for thinner profile and superior electrical performance (e.g., smaller through-hole via inductance). Although advanced substrate materials are available such as low-loss epoxy-based laminates (3M¹⁰) and cyanate ester or epoxy reinforced with PTFE (Gore’s Microlam, Speedboard), stiffness requirements are still major impediments for this coreless technology unless rigid temporary carriers and stiffeners are used. NEC¹¹ and Fujitsu¹² have demonstrated high-density packages with 15 µm lines/spaces. The “carriers” used during buildup have to be removed later by etching or grinding, rendering the coreless substrate process expensive. To overcome warpage during multilayer processing, dielectrics need a high stiffness inorganic reinforcement that makes thinning and laser drilling difficult. A rigid core is still the most common way to make high-density buildup substrates. Although organic laminates may meet the CTE requirements, the high stiffness targets for high-density wiring cannot be addressed with the polymer matrix.

Novel Ceramic Composite Core Substrate

Low CTE inorganic substrates with inherently high stiffness have been widely used during the past few decades. IBM’s glass-ceramic modules can be tailored to match the CTE of silicon and, hence, demonstrate reliability without underfill. Low CTE metal core boards (invar) have shown superior thermomechanical reliability¹³. Metal matrix composites possess many attractive properties such as machinability, high stiffness and thermal conductivity. A few suppliers¹⁴ have developed thin aluminum matrix composite sheets with CTE ~7 ppm/°C and high stiffness (above 220 GPa).

Ceramics like AlN and SiC possess sufficient stiffness and CTEs close to that of silicon to be reliable without underfill. Nevertheless, they are not available in large sizes and are expensive. The ideal substrate material would have the physical properties of ceramics and the large size and low processing cost of organic boards. In addition, it would permit simple, inexpensive machining. A novel manufacturing process (patented by Starfire Systems Inc.) has been demonstrated to yield large-size thin carbon silicon carbide-based composite boards with the required stiffness and Si-matched CTE at low cost. Unlike conventional ceramic technology based on powder processing, this novel technology uses a polymeric precursor¹⁵ to make the ceramic.

This pre-ceramic polymer permits design and fabrication of advanced ceramic matrix composites at low temperatures by polymer infiltration and pyrolysis (PIP) in carbon fibers and fabrics, in large area sheets with the required low CTE and high modulus Figure 6). The in-plane CTE of the boards was measured using a TMA in the range of 0° to 250°C with a ramp of 5°C per minute. TMA data showed the CTE of the sample lies between 2 to 2.5 ppm/°C. The modulus can vary from 80 GPa to 300 GPa, depending on the reinforcement type, fiber content, final hot pressing temperature, and so on. Table 1 summarizes properties of fabricated panels.

The following sections discuss the warpage and dielectric reliability of test vehicles with 100 to 200 µm pitch ICs flip-chip assembled on C-SiC with and without underfill, microvia reliability in metal-via-metal test vehicles, solder joint reliability and Cu-low k compatibility in 100 µm pitch assemblies with and without underfill.

Dielectric reliability. As discussed, the higher dielectric stresses on low CTE boards demand tougher and stronger dielectrics. Test vehicles with the low CTE and high modulus substrates using conventional epoxy dielectric and other advanced dielectrics like benzocyclo butene (BCB), polyimide (PI) and polyphenylene ether (PPE) were fabricated and subjected to accelerated testing to study the warpage and dielectric compatibility of C-SiC boards.

Fabrication was performed on 6 x 6" boards. The ceramic composite boards were laminated with resin-coated copper (RCC) that had thick epoxy (60 to 70 µm). The final soldermask coating used Taiyo PSR 9000 A02 series. Bumped PB-8 dies (flip-chip technology, practical components) were assembled using conventional flip-chip processes both with and without underfill materials. A commercially available fast-flow, snap-cure underfill (Loctite Dexter 4531) was used. TVs with thinner dielectrics were fabricated by first spin coating five to 10 µm thick BCB on the boards. To overcome delamination problems as a result of poor adhesion, BCB was roughened with a suitable oxygen plasma treatment before metallizing with the seed copper layer. Electroplating was followed by stripping of photoresist, etching off the seed layer and soldermasking (25 µm). Finite element models were also developed to validate the experimental observations in selecting suitable dielectric material parameters to minimize the warpage and dielectric cracking. The TVs were subjected to liquid-to-liquid thermal shock tests (-55° to 125°C) for flip-chip on board both with and without underfill. To understand the failure mechanisms, failure mode analysis was done using optical microscopy. Resistance in the daisy chains was checked every 100 shock cycles. Table 2 shows the accelerated testing results for various TVs. While the FR-4 and combination epoxy-dielectric TVs without underfill failed within 100 cycles because of solder joint fatigue, the potential failure mode with C-SiC TVs was primarily dielectric cracking. With thicker epoxy dielectrics, severe dielectric cracking was observed at the corners of the square soldermask openings near the test pads and daisy chain, and along edges of the soldermask openings. These cracks originate from the stress concentration at the corners of the square openings and are also seen to penetrate through the copper traces. Cracks within the copper traces, independent of dielectric cracking, were also observed within the soldermask openings when the stiffness of board was low (<80 GPa). Boards with moderate stiffness of 150 to 170 GPa (C-SiC²) also showed some dielectric cracking. With thinner (BCB), low CTE (PPE), high-strength (PI) dielectrics, no dielectric cracking was observed in the TVs as compared with thicker epoxy buildup. Simple analytical models indicate that the dielectric stress is a function of CTE mismatch, film modulus and temperature drift from the stress-free temperature. More accurate FEM models capture the role of dielectric thickness at the corner of soldermask openings and can better explain the dielectric behavior in different test vehicles.

Figure 7 shows the dielectric stresses for buildups with different thickness and type of dielectrics. Figure 8 shows the dielectric stresses for 60 µm epoxy buildup are quite high, ranging from ~75 to 90 MPa in the stress concentrated areas with an average of ~53 MPa over the whole dielectric. These stresses drop to ~69 to 82 MPa with an average of ~25 MPa for 6 µm BCB buildup. For a 30 µm buildup with PPE with a low CTE (13 ppm/°C) dielectric, the dielectric stresses as shown in Figure 8 are minimal, averaging ~6 MPa. Stress concentration areas in dielectrics are at the pad corners leading to the observed dielectric cracking. Both FEM results and experimental observations confirm that this is more predominant when high CTE thick dielectric was used for the buildup. Therefore, it can be inferred that the dielectric thickness and its CTE are the major factors contributing to the failure modes. Tough, strong polyimides did not show cracking under the same lamination and buildup geometries while epoxies showed severe cracking. Dielectrics such as polyimide and PPE showed lower stresses compared to thick epoxies and are relatively tougher than epoxy (Table 3). This explains the vastly different behavior of dielectric cracking with different buildups.

To further analyze these failure mechanisms, in-situ warpage (Akrometrix) was measured to monitor the substrate behavior during thermal cycling. A moderate stiffness inorganic (C-SiC) substrate with 80 GPa (1 mm) stiffness showed a warpage changing from 6.5 µm/in. at 100°C to 13 µm/in. at -55°C. These substrates showed severe dielectric cracking along soldermask openings and corners. These cracks are also seen to penetrate through copper lines. A carbon fiber epoxy-based low CTE board (5 ppm/°C) with the same stiffness showed much higher warpage (15-25 µm/in.) during thermal cycling, which in conjunction with the dielectric stresses resulted in dielectric cracking and bump pull-off leading to electrical failures. The warpage in this case was abnormally high and did not follow trends expected from simple thermomechanical warpage models. It is interesting to note that similar warpages on FR-4 substrates did not result in dielectric cracking presumably from the relatively lower dielectric stresses. The higher stiffness and thicker ceramic composite boards (C-SiC 2 mm) with 150 GPa modulus showed much less warpage than C-SiC 1 boards, with a minimum of 1 µm/in and maximum of 2.1 µm/in. during thermal cycling. In these ceramic composite boards, dielectric cracks were only seen at the corners and interfaces, which are stress concentration regions. The high stiffness ceramic boards did not show any cracking with thinner buildup. With thicker buildup, some cracking was observed, but did not result in electrical failure. The cracking in the dielectrics correlates well with the in-situ board warpage. Cyclic warpage is expected to accelerate crack initiation and crack growth at the stress concentration regions. Figure 9 shows experimental results. These results are in agreement with the previous work published by Shinotani et al¹⁶.

Copper microvia cracking is another important concern for high-density wiring at fine pitch. Simulation results for plated copper microvia diameter (25 µm) and different dielectric layers signify that the copper microvia strains after thermal cycling are least in the case of low CTE dielectrics (1.4% with PPE dielectric) and highest in the case of epoxy (7.5%), with microvias in BCB in the intermediate range (5.1%). The microvia strains for (C-SiC 3/epoxy) are higher than the experimentally measured¹⁷ yield-strain value of acid-plated copper, which is 7.4%, indicating that the copper in this case is in the plastic region and has a higher probability of failure during fatigue testing. The models also indicate that, with everything else remaining the same, the higher the dielectric CTE, the more strains are induced in the copper after thermal cycling. This observation agrees with the results previously reported¹⁸. On the basis of numerical modeling, the smallest microvia is expected to survive the least number of thermal cycles in accordance with the previous works¹⁹. With finer via structures, copper hardens because of the high plastic strain gradients. Therefore, the trend of increased via strains with decreasing via diameter may not be as severe as shown here, and the fatigue life may be higher than predicted from this strain analysis. The microvia (fabricated in diameters up to 25 µm) structures on C-SiC substrates), survived 1000 cycles of -55° to 125°C air-to-air thermal cycling without any failures.

Solder Joint Reliability

Test vehicle fabrication. Georgia Institute of Technology and Institute of Microelectronics/National University of Singapore (IME-NUS) collaboratively designed substrates with 100 µm pitch on a 2 x 2 cm die and substrate with appropriate routing and testing pads. The substrate fabrication was done by first laminating a polyimide film from DuPont on the C-SiC boards to insulate and planarize the surface. Polyimide was chosen because of its high strength and elongation to failure. This was followed by the semi-additive buildup process to form the copper metal layer (5 µm) on polyimide. Ciba LM-7081 was spin-coated to form a 4 µm thick layer of soldermask. NiAu surface finish was used as the TSM (top surface, etallurgy) of the bonding pads. Peripheral area flip-chips (20 x 20 mm) with three rows of Sn-0.7Cu solder bumps at 100 µm pitch from TLMI were then assembled with and without underfill to complete the fabrication of the TV. Figure 10 shows a completed TV along with the daisy-chain design layout. Reliability was evaluated with air-air thermal cycling tests from -40° to 125°C. Each daisy chain’s DC resistance was measured after every 100 cycles.

Reliability results. The plastic strain in the solder joint increases as the CTE of the base substrate deviates from that of silicon. FEM models indicate that FR-4 shows the highest plastic strain range (~0.10) while the C-SiC boards showed low plastic strains (<0.01), indicating these boards are ideal for high-reliability solder joints. C-SiC TVs did not show any change in resistance after 1,000 cycles. The experimental results are in accordance with modeling expectations as summarized in Table 4. TVs with polyimide planarization and 5 µm thin epoxy soldermask were cross-sectioned for signs of cracking in the copper lines or buildup layers. No cracking in the solders was observed (Figure 11). With a suitable combination of dielectric materials and buildup geometry, the C-SiC substrate showed complete system-level reliability with potential to address much higher wiring and interconnection densities.

Summary

A novel ceramic composite board material, C-SiC, addresses the need for ultra-high-density multilayer wiring to route high I/O counts, enable reliable Cu-low k ICs and also provide reliable fine-pitch interconnections between the IC and package. An integrated SOP package with embedded components and digital, RF and optical functions requires ultra-low-loss, low-stress, high-strength dielectrics that have stable electrical properties over a wide range of frequency and temperature.

Experimental results were corroborated with FEM modeling results. The high stiffness C-SiC boards with thinner BCB dielectrics did not show failures related to dielectric cracking or solder joint fatigue. While finer via diameters could aggravate the microvia strains, a combination of low CTE and high-strength dielectrics can address the reliability problem in multilayered structures. The proposed high-performance ceramic composite substrate material in combination with ultra-low-loss dielectrics showed the required attributes for solder joint reliability, dielectric reliability, low warpage and microvia reliability for the fabricated two-metal layer system. C-SiC boards also exhibit low via-pad misregistration, making them suitable for building multilayered structures on a larger area with smaller via capture pads. In addition, the manufacturability of these boards enables them to be cost-effectively produced in large volumes. These boards have the potential to be the ideal candidate board materials for next-generation high-density packaging requirements.

Acknowledgments

This project is funded by National Institute of Standards and Technology through its Advanced Technology Program. 

References

1. R.R. Tummala, “Moore’s Law Finds Its Match,” IEEE Spectrum, June 2006.
2. V. Sundaram, R.R. Tummala, F. Liu, P.A. Kohl, J. Li, S.A. Bidstrup-Allen and Y. Fukoka, “Next-Generation Microvia and Global Wiring Technologies for SOP,” IEEE Transactions on Advanced Packaging, May 2004, pp. 315-325.
3. public.itrs.net.
4. S. Banerji, P. Markondeya Raj, S. Bhattacharya and R.R. Tummala, “Warpage Induced Limitation of FR4 and Need for Alternate Materials for Microvia and Global Interconnect Needs,” IEEE Components Packaging and Manufacturing Technology (CPMT) Transactions on Advanced Packaging, vol. 28, no. 1, February 2005, pp. 102-113.
5. Atsushi Takahashi, Kazuhito Kobayashi, Shigeharu Arike, Norio Okano, Hajime Nakayama, Akihiko Wakahayashi and Takayuki Suzuki, “High Density Substrate for Semiconductor Packages Using Newly Developed Low CTE Build Up Materials” International Symposium on Advanced Packaging Materials, March 2000, pp. 216-220.
6. D.J. Alcoe, M.A. Jimarez, G.W. Jones, T.E. Kindl, J.S. Kresge, J.P. Libous, R.J. Stutzman, and Cheryl L. Tytran-Palomaki, “HyperBGA: A High Performance, Low Stress, Laminate Ball Grid Array Flip Chip Carrier,” MicroNews, second quarter 2000, vol. 6, no. 2, pp. 27-36.
7. S. Khan, C.G. Gonzalez, M. Weinhold, “Organic, Non-Woven Aramid Reinforced Substrates with Controlled In-Plane CTE Means More Reliable Solder Joint Reliability,” Advances in Electronic Packaging, vol. 2, 2001, pp. 1345-1362.
8. T.S. Krziwanek, “Low CTE materials for Printed Wiring Boards,” International Symposium on Advanced Packaging Materials Proceedings, March 2001, pp. 175-180.
9. Prismark Partners LLC, The Electronics Industry Report 2002.
10. Shichun Qu, Guoping Mao, Fuming Li, Robert Clough, Nelson O’Bryan and Robin Gorrell, “A New Organic Composite Dielectric Material for High Performance IC Packages,” Electronic Components and Technology Conference Proceedings, May-June 2005, pp. 1373-1377.
11. Jun Sakai, Tadanori Shimoto, Koichiro Nakase, Kazuhiro Motonaga, Hirokazu Honda and Hirobumi Inoue, “Signal Integrity and Power Integrity Properties of FCBGA Based on Ultra-Thin, High-density Packaging Substrate,” Electronic Components and Technology Conference Proceedings, May-June 2005, pp. 284-290.
12. Masateru Koide, Kenji Fukuzono , Hideaki Yoshimura, Toshihisa Sato, Kenichiro Abe, Hidehiko Fujisaki, “High-Performance Flip-Chip BGA Technology Based on Thin-core and Coreless Package Substrate,” Electronic Components and Technology Conference Proceedings, May-June 2006, pp. 1869-1873.
13. K. Nakamura, M. Kaneto, Y. Inoue, T. Okeyui, K. Miyake and S. Oota, “Multilayer Board with Low Coefficient of Thermal Expansion,” 33d International Symposium on Microelectronics Proceedings, September 2000, pp. 235-240.
14. pcc-aft.com, alsic.com.
15. starfiresystems.com.
16. K.-I. Shinotani, P. Markondeya Raj, M. Seo, S. Bansal, H. Sakurai, S. K. Bhattacharya and R. Tummala, “Evaluation of Alternative Materials for System-on-Package (SOP) Substrates,” IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 27, no. 4, December 2004, pp. 694-701.
17. G. Subbarayan, K. Ramakrishna, B.G. Sammakia and P.C. Chen, “Mechanical Integrity of Vias in a Thin-Film Package During Manufacture, Assembly and Stress-Test”, 1993 Electronic Components and Technology Conference, pp. 276 – 279, June.
18. G. Ramakrishna, F. Liu and S.K. Sitaraman, “Role of Dielectric Material and Geometry on Thermo-Mechanical Reliability of Microvias” Electronic Components and Technology Conference, May 2002, pp. 439-445.
19. S. Hegde, R. Pucha and S. K. Sitaraman, “Enhanced Reliability of High Density Wiring (HDW) Substrates through New Base Substrate and Dielectric Materials,” Journal of Material Science: Materials in Electronics, vol. 15, no. 5, May 2004, pp. 287-296.

Nitesh Kumbhat, P. Markondeya Raj, Raghuram V. Pucha, Venky Sundaram, S. Sitaraman and Rao R. Tummala are with the Georgia Institute of Technology (Georgia Tech) Packaging Research Center (gatech.edu). Contact Raj at raj@ece.gatech.edu. Ed Bongio is with Starfire Systems Inc.

• Prev
• Next