An elegant etching and metallization process for inserting and interconnecting tiny chips.

A new and somewhat daring method for packaging devices is under development at an unknown number of locations in the U.S. and U.K., and probably in other parts of Europe as well. The new technology involves etching a pit of the correct depth and size in the surface of a silicon wafer, then inserting a tiny patterned chip (sometimes called a “chiplet”) into the pit. The chiplet is then interconnected with other nearby chiplets (Figures 1 and 2).


The overall purpose of this approach is to build what amounts to a low-cost multichip module at the wafer level. Some early research has placed silicon chiplets into pits on an unpatterned silicon wafer, but a good deal of work also has been done in inserting chiplets of multiple species – silicon, GaAs, InP – on the same wafer. For applications involving laser, high frequencies, or high power levels, this opens up the possibility of placing silicon and III-Vs chiplets, as well as chiplets of other species, onto the same substrate.

Dr. Vincent Fusco at Queen’s University, in Belfast, Northern Ireland, is carrying out advanced work in this area. He uses 4" silicon wafers, into which he etches pits for inserting the smaller chiplets. To date he has used both GaAs and silicon chiplets. He has concentrated on the key processes – etching the pit, inserting the chiplet, and bonding the chiplet in place – and works at this point with whole wafers, without dicing the wafers into individual die.

The silicon wafer that is the substrate typically has a thickness of around 500 µm. The chiplets are of various sizes. GaAs chiplets range in size from about 1 x 1 mm to 2 x 3 mm; silicon chiplets are more variable in their dimensions. For etching the pits into which the chiplets will be inserted, the thickness of the chiplet is the most important factor, since Dr. Fusco interconnects the chiplets using standard photolithographic procedures for top-level metallization. GaAs chiplets, made by commercial foundries to Dr. Fusco’s design, have a standard thickness of about 100 µm, but silicon chiplets have variable thicknesses and must be measured before etching the pits.

The most difficult process is controlling the etched pit depth. Once the chiplet thickness is known, Dr. Fusco is able to control the depth of the pit to within a few microns, a degree of accuracy sufficient for successful metallization.

Etching precisely the right depth so that the top surface of the chiplet and the top surface of the silicon wafer are vertically within a micron or two of each other is difficult. By thoroughly characterizing the etching process, Dr. Fusco has been able to make the process highly repeatable.

Dr. Fusco selected the metallization process for interconnecting the chiplets because of its inherent simplicity. He notes that the interconnects could also be formed by spinning a relatively thick resist onto the wafer to accommodate greater height differences, and then laser-drilling and plating vias through the resist, but this method would add processing steps and increase complexity. Some researchers have interconnected chiplets with wire bonds, but Dr. Fusco theorizes that the metallization process he uses is less harmful to the chiplets than thermosonic wire bonding.

Another critical step is bonding the chiplet within its pit. In early work, Dr. Fusco etched a hole in the bottom of the pit all the way through the silicon wafer, and then fastened the chiplet with an epoxy, but this bonding method had obvious thermal limitations. Currently, after etching the pit, Dr. Fusco carries out a second etch from the back of the wafer to form a via leading to the bottom of the pit. After the chiplet has been inserted into the pit, and temporarily stabilized by tape, copper is electroplated into the via, using the back metal contact as the seed layer.

The result is what amounts to a copper plug beneath the chiplet (Figure 3). The diameter of the plug is roughly half the diameter of the chiplet. The plug performs two functions: It holds the chip in position and acts as a heat removal device.


One of the reasons Dr. Fusco prefers to add a layer of metallization to interconnect chiplets is that the metallization can be laid across the small gap that typically exists between the sides of the chiplet and the walls of the pit. The pit, in other words, needs to be oversized by a few µm to simplify insertion of the chiplet. In actual production, Dr. Fusco doesn’t foresee a need to fill this gap. Bridging the gap with metallization is similar to techniques used in MEMS devices to make floating beams.

Throughout his research, Dr. Fusco has aimed at devising simple production processes that will reduce costs and promote high performance reliability in the finished system. In his current work, Dr. Fusco may design, for example, an amplifier or a mixer, probably in GaAs. He would then insert the GaAs chiplets into a silicon wafer. The high resistivity silicon substrate permits very low microwave-loss interconnects between the GaAs chiplets.

The resulting die is a miniaturized MCM, in which the silicon die/substrate holds the GaAs chiplets. The doped high resistivity (3,000 V) silicon wafer becomes a structural member and provides the means for holding chiplets in etched pockets in precise mechanical positions. Use of high resistivity silicon minimizes crosstalk and similar coupling effects between the system and substrate via the interconnect system. In theory, it would also be possible to put diodes and switching elements into the silicon substrate. Suitable real-world products using GaAs chiplets would include low-cost broadband millimeter-wave wireless systems, and low-cost millimeter-wave radar-type sensors.

He anticipates that in full-scale production the use of chiplets would achieve both low cost and low failure rates. Compared to a conventional MCM, for example, Dr. Fusco’s GaAs-chiplets-on-silicon have simpler interconnects and far fewer overall process steps.

The number of chiplets that could be inserted into an individual die could, if needed, be quite large. For example, the GaAs chiplets that Dr. Fusco inserts are typically 1 x 1 mm, while some large silicon die reach 40 x 40 mm. It is not yet known whether there would be a need for a chip having scores or more of chiplets, or whether such a design would even be feasible. Smaller die employing a few chiplets of a few different species would probably be more realistic.

The combination of rapidly developing technologies such as redistributed interconnecting systems (currently being researched in wafer-scale packaging) and chiplet technology makes feasible the possibility of an “all silicon MCM.” A full system of standard off-the-shelf silicon devices (thinned to a controlled thickness level at wafer stage), along with chiplets of other species, could be inserted into cavities etched into the wafer surface of a silicon wafer. These could then be interconnected by redistribution techniques into a complete system.

The simplicity of design, the minimal use of differing materials and almost a complete matching of expansion coefficients add up to potential gain in cost and reliability in the sophisticated high-end applications.

The possibility also exists – and this is purely speculation – that GaAs, silicon or other chiplets could be added to one region of a silicon die, the rest of which was covered by standard silicon circuitry. There may be design or packaging advantages, for example, in dedicating one corner of a silicon die to a GaAs chiplet for high-frequency needs.

Contact Professor Vincent Fusco at Queen’s University Belfast Electronics, Communications Information Technology (ECIT); v.fusco@ecit.qub.ac.uk. Keith Gurnett and Tom Adams are freelance writers; teadams@earthlink.net.

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