Agilent Technologies Inc. (Palo Alto, CA) has introduced its Versatest series Model V5400 to deliver a low cost of test across a full spectrum of memory devices. According to the company, the model's algorithmic pattern generator (APG) and patented tester-per-site (TPS) architecture provide configuration flexibility and up to four times improvement over existing systems in throughput for wafer sort and final memory testing.

Compatible with Agilent's model V4400, the newer version overcomes the challenge of testing standard and stacked memory modules such as flash, DRAM and SRAM while offering up to 4,608 channels and 144 independent test sites. The increased performance and lower system costs helps reduce the overall cost of test for semiconductor contract manufacturers, fabless design houses and memory integrated device manufacturers.

The growing consumer demand for digital devices with added functionality and smaller footprints at lower prices has given rise to new test challenges. The devices require higher frequency test systems and the flexibility to test multiple types of memory such as flash and DRAM concurrently, while continuing to require a lower cost of test. Agilent's single, scalable platform architecture will allow users to test standard memories, reduced pin-count devices, BIST-enabled devices and stacked memories.

Agilent's TPS architecture makes it possible for each device under test (DUT) to receive its own set of tester resources. The APG on the test site module has the ability to maximize tester resources based on the needs of the DUT. Dynamic APG can independently test up to four low-pin-count DUTs per site module. For complex tests or high pin count devices, APG can reallocate all site module resources toward testing a single DUT. Configurable solely through software, the APG enables the model to test devices without a change in tester hardware.

www.agilent.com