The SMTA seeks abstracts for the 2nd Annual International Wafer-Level Packaging Congress and Exhibition (IWLPC).  The event, scheduled for Nov. 3-4 in the San Jose Doubletree Hotel, will track leading-edge IC packaging and test technologies with special emphasis on 3-D stacked packaging.
 
200-word abstracts are being accepted through April 1 for two tracks, Wafer-Level Packaging (WLP) and 3-D Stacked Packaging/Chip-Scale Packaging.
 
For more information:
http://www.smta.org/iwlpc/call_for_papers.cfm

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