Screen Printing
How lesser-known printer software features can improve process control.
As a process engineer specializing in the stencil printing operation, I understand why many operators are unaware of the bells and whistles in advanced printing platform software – especially when working in a busy production environment. While the primary focus is speed, pressure and angle to ensure the best print at the fastest cycle time cadence, sometimes the production pace can be interrupted by unexpected events. I was reminded of this – and a couple of software tricks – recently when doing evaluation work in our lab.
A “rougher” foil may improve stencil performance.
A high-performing stencil printing process deposits the right amount of material volume in the right place, at the right time, and at the lowest cost per print achievable. Every assembly professional strives for this utopia, leaving no solder paste stuck in the apertures or smeared on the underside of the stencil. Naturally, with all the variables, this state is difficult to achieve 100% of the time. A perfect gasket (board to stencil) does not exist in the electronics manufacturing real world. Transfer efficiency is managed through aperture designs to provide the desired material volume on the pad, and solder paste smear (or its potential) is alleviated by cleaning the underside of the stencil between prints to avoid bridging. Cleaning, of course, comes at a cost – both in consumables use and in production time. If more high-quality prints can be achieved between necessary cleans, consumables overhead will be lower and throughput will be higher.
The top eight fixes in the fishbone diagram to get back in spec.
The last column focused on making a “green light” stencil printing process more efficient, but for a not-so-green – maybe a bit more amber – print operation, some tried-and-true troubleshooting methodologies can get high-yield boards moving again. As I’ve noted before, myriad stencil printing inputs can affect outcomes. The famous fishbone diagram, noted in FIGURE 1, can seem daunting at first, but by taking a methodical approach to understanding the root cause of a problem, it’s relatively straightforward to get printing back in spec.
The time to squeeze out more efficiency is when everything is in spec.
What kind of approach do you generally take? Do you follow the “if it ain’t broke, don’t fix it” mantra, or are you more the “it’s good, but it could be better” type? In electronics manufacturing, continuous improvement is often discussed, but how much does your organization adhere to this philosophy when the shop floor is humming and everything is within spec? This is when process engineers should try to squeeze out even more efficiency.
Certainly, there is urgency around a process that is not running as it should. However, when all the lights on the line are green, there is likely opportunity for more improvement than you realize. Consider challenging the process through the lenses of incremental cost reduction and quality enhancement.
In the stencil printing process, there are several possible avenues for lowering cost and raising quality, even when everything is within spec:
Cost down. The first and most obvious area for resource optimization is understencil cleaning. This sub-process of stencil printing has several costs associated with its operation, including time (output reduction) and a fixed cost (fabric and solvent consumables) for every clean. A majority of print platform suppliers ship equipment with relatively liberal default settings for fabric advance (how much is used for each clean) and solvent volume. This is based on assumptions a manufacturer may be cleaning a very dirty stencil with numerous apertures across the entire length of the fabric, so high debris removal must be accommodated. In essence, the defaults are set for worst-case scenarios, as is fairly standard practice. Optimizing these settings based on specific process conditions has the potential to reduce waste through streamlined consumables delivery.
Protecting modern-day, complex stencils requires a mechanism overhaul.
Ahh, understencil cleaning: a necessary – but challenging – aspect of the stencil printing process. I’ve certainly discussed cleaning in this space before, as the topic bears revisiting when things change. Now is one of those times. As a subprocess of the overall printing operation, understencil cleaning is employed at specific intervals – after “x” number of prints, as determined by the process and the product details – to clear the aperture area of solder paste. Left unchecked, there is a high probability any smear around the aperture will cause defects. This is especially true if printing anything close to microelectronics-level dimensions such as 0402s, fine-pitch BGAs, etc. With these conditions, the likelihood of bridging, solder balling or some form of defect is relatively high without a robust understencil cleaning regimen. To maintain a centered, high-yield process, thorough cleaning of the underside of the stencil between prints “as and when” is required. (There is no standard, “right” number.)
These facts have not changed in many years. What has changed are PCB designs, dimensions and electronics assemblers’ expectations. As we are all aware, miniaturization has driven stencil thicknesses down to an almost unbelievable 60µm for today’s mobile products. That’s thin! Modern-day stencils are highly complex tooling components with many tens – if not hundreds – of thousands of apertures cut into a paper-thin piece of stainless steel. The material is delicate, to say the least. With these actualities, it is time to reconsider the mechanisms for ensuring thorough, repeatable understencil cleaning that do not damage the stencil, introduce instability into the process or take too long to perform routine tasks. The industry should rethink the understencil cleaning system needed to manage current and future assembly realities. Aspects to consider include:
How using a thinner stencil corrected transfer efficiency.
SMT specialists are intimately familiar with the guiding rule of stencil printing: the area ratio. The correlation between stencil aperture dimensions and the predictability of solder paste transfer efficiency is well understood, and IPC has standardized design guidelines outlining ideal conditions. The accepted area ratio for maximum transfer efficiency is approximately 0.60, which is a function of the aperture open area and aperture wall area (stencil thickness). When the area ratio falls below the recommendation, challenges arise.
Reaffirmation of the relevance of the area ratio rule occurred recently when our company was asked to analyze a customer assembly where bridging was observed. The printing dimensions of the PCB’s bridging area were tight. The 01005 apertures measured 200µm x 200µm, the stencil thickness 80µm and the interspace about 150µm. So, while not at the bleeding edge like some newer-generation designs, the board was nevertheless challenging. With these aperture dimensions, the area ratio was an acceptable 0.63. The volume of paste on pad was 2.08 nanoliters (NL), and the standard deviation was less than 10%, but SPI analysis revealed bridging.
For its part, the customer had logically attempted to lessen the bridging propensity by narrowing the aperture width to reduce the amount of solder paste being transferred onto the pad. Unfortunately, doing so resulted in conflict with the area ratio rule, and taking this route ultimately impacted repeatable transfer efficiency.
