PHARR, TX ― ROCKA Solutions is set to present at the SMTA Pan Pacific Microelectronics Symposium, scheduled to take place Jan. 29 - Feb. 1, 2024 at the Big Island of Hawaii. The presentation, titled "Elevating Excellence in High-Reliability Electronics: The Personal and Lasting Legacy of Clean PCBs," will be delivered by Justin Worden, VP Sales & Marketing at ROCKA Solutions.
In the realm of printed circuit board (PCB) production, the saying "Business is Personal, and our legacy lives through the products we produce" holds profound meaning. Each PCB manufactured by ROCKA Solutions reflects a commitment to quality, reliability and the enduring legacy created in the dynamic world of electronics. Worden's presentation will delve into the profound significance of clean PCBs, emphasizing the critical role meticulous post-reflow cleaning plays in achieving excellence in high-reliability electronics.
The presentation will explore the essence of "Business is Personal," extending beyond monetary transactions to encapsulate the dedication and responsibility manufacturers bear to deliver products that withstand the test of time. Clean PCBs, free from soldering residues and contaminants, are not just a technical requirement but a personal commitment to excellence. The legacy of a manufacturer is inherently tied to the products they produce, and by prioritizing clean PCBs, manufacturers invest in the longevity and reliability of their creations.
The presentation will conclude with a powerful reminder that manufacturing high-reliability electronics is not just a commercial endeavor but a deeply personal commitment to quality, safety, and excellence. Clean PCBs, as the cornerstone of this commitment, uphold the legacy of trust, reliability, and exceptional quality.
"ROCKA Solutions is excited to share insights on the crucial role of clean PCBs in high-reliability electronics at the SMTA Pan Pacific Microelectronics Symposium," said Worden. "Our commitment to excellence extends beyond business transactions; it's a personal pledge to deliver products that stand the test of time."
WASHINGTON – The Semiconductor Industry Association (SIA) today released the following statement from SIA President and CEO John Neuffer in response to the semiconductor manufacturing incentives announced today by the U.S. Department of Commerce and Microchip Technology. The incentives, which are part of the CHIPS and Science Act, will support Microchip’s manufacturing projects in Colorado and Oregon.
“Today’s announcement will help propel semiconductor manufacturing projects in Colorado and Oregon and reinforce America’s chip supply chains for critical automotive, medical, aerospace, and defense technologies, among other applications. We congratulate Microchip on advancing these important projects and commend the progress made by Secretary Raimondo and the CHIPS Program Office team in beginning to distribute CHIPS incentives. We look forward to seeing more projects receive vital CHIPS funding to help reinvigorate America’s economy, national security, and critical supply chains.”
The CHIPS Act’s manufacturing incentives have already sparked substantial investments in the U.S. In fact, companies in the semiconductor ecosystem have announced dozens of new projects across America—totaling more than $200 billion in private investments—since the CHIPS Act was introduced. These announced projects will create more than 40,000 jobs in the semiconductor ecosystem and support hundreds of thousands of additional U.S. jobs throughout the U.S. economy.
WASHINGTON – The Printed Circuit Board Association of America applauds the Pentagon's recently announced $46.2 million award to an American company to produce the latest integrated circuit substrates, high-density and ultra-high-density interconnects and advanced packaging.
The millions of dollars being distributed by leaders at the Pentagon are an important first step. But this critical industry requires investments and tax incentives in billions – not millions – to restore America’s leadership position in microelectronics.
Chips don’t float.
Despite semiconductors’ rockstar status they are only one third of the technology stack.
New chips produced in the U.S. funded by the CHIPS Act will still end up being shipped to Asia to be packaged with substrates and PCBs…made in Asia. We are exacerbating the supply chain issue by not addressing the entire technology stack.
Today every defense system is dependent on microelectronics. It is time for Congress to provide support for American-made microelectronics beyond semiconductors.
Without further investments in printed circuit boards, substrates, and the ability to do advanced packaging, our national and economic security remains at grave risk.
CLINTON, NY – Indium Corporation Senior Area Technical Manager Jason Chou is set to deliver a presentation at the Power Device & Module Expo, held in conjunction with NEPCON Japan, on January 24 in Tokyo. The presentation will explore trends in EV power electronics and the interconnect materials that enable them.
Interconnect materials play a major role in the efficiency and reliability of power electronics. The adoption of state-of-the-art wide bandgap die technologies such as SiC and GaN, require complementary die-attach materials to maximize the benefits. Higher power densities require new strategies for thermal management and heat dissipation. Packaging trends such as transfer molded modules and the direct bonding to heat-sinks and coolers is an area where different material and process options are considered, each with pros and cons for addressing the challenges of this application.
“As the world moves toward a greener, more sustainable future, the automotive industry is at the forefront of this transformation. EVs have emerged as a key solution for tacking carbon emissions which contribute to climate change, and at the heart of every electric vehicle are power electronics,” said Chou. “In this presentation, I will cover breakthroughs and trends that are shaping the power electronics landscape, especially for EVs.”
As senior area technical manager in Taiwan, Chou provides technical support to customers with a focus on the semiconductor industry. He has 10 years of industry experience, including specialization in front-end wafer fabrication processes, thin-film modules, and defect analysis for wafer metrology. Chou earned a master’s degree in Chemistry from National Tsing Hua University and a bachelor’s degree in Chemistry from National Cheng Kung University. He served as the group leader for the National Nano Device Laboratory, Tainan, Taiwan, where he collaborated with university professors and industry professionals on special projects for semiconductor manufacturing.
PARAMOUNT, CA – An exciting 2023 year comes to a close for the team at Excellon Automation Company. Excellon’s president, Bailey Su, relays “We turned on operations at our newly designed manufacturing facility, added new product lines, and increased staffing in the key areas of engineering, production, and service in North America. The changes we’ve implemented throughout this past year are definitely making us more competitive in the PCB manufacturing space.”
The layout of Excellon’s new facility located in Paramount, California, was designed to enhance the multiple, parallel threads of sub-assembly manufacturing. An increase in the capacity of such concurrent processes, feeding into the final assembly stage, has dramatically reduced production lead-times. A new MRP system has also been integrated to better drive material flow plans and production schedules. According to Nghia Tran, production manager, “With the implementation of our new strategy, production schedules have shown a 15% improvement in lead-time reduction.”
All Excellon systems are designed and manufactured in California. Product lines include mechanical drill and drill-router platforms (single to six spindle configurations) and the COBRA II laser systems. Excellon also offers spindle rebuild and electronics repair services at the IER operations in Riverside, California.
SAN DIEGO, CA – Chiplet Summit announces its initial keynote schedule with emphasis on AI applications. The second annual Chiplet Summit, to occur on February 6-8 at the Santa Clara Convention Center, has now set its initial keynote schedule.
Speakers will be:
There will also be short talks by the UCIe Consortium, Silicon Catalyst, and SNIA.
Keynote topics will include AI solutions, design methods, memory, interfaces, new packaging methods, and the open chiplet economy. Attendees will learn how chiplets can make the latest designs take less time, cost less, and be more scalable. Presentations will focus on handling AI applications, such as ChatGPT®.
Summit General Chair Chuck Sobey says, “At our keynotes, attendees hear what industry leaders are planning. AI is an obvious driver everywhere. It requires huge amounts of memory, fast low-latency connections, and the ability to do both training and model execution at top speed. Making it work well takes engineering and R&D that covers all chip design stages.”