Intel Validates Chip-to-Chip Interconnection
Published: 16 August 2006
by Staff
SAN JOSE -- The performance potential of high speed, copper based, direct interconnections between IC packages by means of a flexible circuit was validated by Intel Corp. in July at the IEEE CPMT Society's ECTC conference.
A paper, Flex-Circuit Chip-to-Chip Interconnects, was authored by team of scientists and engineers from facilities in Hillsborough, OR, Santa Clara, CA and Chandler, AZ. The authors concluded that “20 Gbps signaling on channels of relevant lengths is possible,” but noted that “we are not ready to introduce flex I/O into any mainstream products.” Even so, they did conclude that “the possibility of a chip-to-chip interconnect with minimal discontinuities and propagation loss is a strong attractor and corresponding high-speed solutions will be in demand.”
“We are delighted with both the quality of the Intel team's research and their reported results” noted SiliconPipe CEO and co-founder Joseph Fjelstad, “These results (20Gbps over extended distance) add significant credibility to SiliconPipe's concepts and validate the results SiliconPipe has presented to the electronics industry over the last few years, most recently in February at DesignCon West.”
SiliconPipe OTT technology (an acronym for Off-the-Top or Over-the-Top) can enable high-speed data requirements and low power potential.
“In our demonstration vehicle, code named Sidewinder, our team showed it possible to send signals at 10 Gbps over distances up to 30 in. through two connectors and do so using less than 2% of the anticipated transmission power while maintaining a 60% timing margin,” Fjelstad said. “However, there is still more benefit to mine and extract in this area and SiliconPipe is continuing to develop and evaluate new copper based interconnection solutions to meet the cost performance needs of future electronics and the Stair Step Package it appears will be an important element of that future.”
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