Forefront
Does Moore’s law apply to the new HI frontier?
The IEEE International Electron Devices Meeting (IEDM) held a night panel discussion on Dec. 10 titled Rest in Peace Moore’s Law, Long Live AI. As the title suggests, the discussion focused on the future of computing and the role of hardware. The moderator proposed questions like will CMOS technology become commoditized and differentiation occur mostly in circuit design, algorithm and architecture development? Will special purpose coprocessor adoption rates accelerate beyond CPUs and GPUs? What is the role of heterogeneous integration in the AI hardware ecosystem? Will the traditional memory hierarchy be upended by the arrival of non-volatile memory? Will analog accelerators using non-volatile memory elements drive the future semiconductor roadmap as scaling slows, enabling exponential improvements in compute efficiency and performance? Not all the questions were answered, but the discussion was lively.
Whether round or rectangle, HDI will be required to meet the needs of next-generation semiconductor nodes.
The annual ECTC revealed exciting advancements on single- and multi-die packages.
The IEEE Electronics Components and Technology Conference (ECTC) at the end of May welcomed nearly 1,500 attendees to the sunshine state of Florida to discuss the latest developments in electronics packaging technology.
A panel discussion on the first evening focused on the topic Panel Fan-Out Manufacturing: Why, When and How? The panel was designed as a jury, with a customer (Qualcomm) surrounded by round wafer proponents (TSMC, Amkor’s Nanium) on one side and panel proponents (Deca Technologies, IZM Fraunhofer consortium) on the other. No conclusion was reached regarding the “right” path to meet customer requests for lower-cost packaging (in this case Qualcomm), but clearly panel processing could be an option. Exactly when panels would move into high-volume manufacturing remained a mystery, but in the audience representatives from Samsung Electro-Mechanics (SEMCO) watched carefully for the reaction. SEMCO continues its development of a panel line, while Nepes and Powertech Technology (PTI) indicate lines are ready. Unimicron continues its research on panel processing and presented a paper discussing stress and warpage for its RDL-first panel FO-WLP.
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