Updates in silicon and electronics technology.

Ed.: This is a special feature courtesy of Binghamton University.

IBM announces 2nm GAA-FET technology. IBM announced its 2-nanometer CMOS technology, developed at its Albany research center. The development has technical firsts: the use of bulk Si wafers with bottom dielectric isolation under the nanosheet stack; reducing leakage and enabling 12-nnm gate lengths; a second-generation inner spacer dry process for precise gate control; FEOL EUV patterning to allow nanosheet widths from 15 to 70nm; and a novel multi-Vt scheme. This technology is expected to give a 45% performance boost or 75% power reduction, compared with the 7nm. (IEEC file #12324, Semiconductor Digest, 6/11/21)

Light-based method creates 2-D polymer. Linköping University researchers developed a method that uses light to manufacture 2-D polymers that have the thickness of a single molecule and could create a path for the development of ultra-thin, functional 2-D materials with highly defined crystalline structures. Using an on-surface photo-polymerization process, they tested a way to manufacture a 0.5nm-thick, 2-D polymer consisting of several hundred thousand molecules identically linked. The two-step method takes advantage of the self-organizing properties of fluorinated anthracene triptycene molecules. Because the polymerization takes place in a vacuum, the material is protected from contamination. The 2-D polymer film is stable under atmospheric conditions. (IEEC file #12370, Photonics Spectra, 7/14/21)

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A study of the behavior of flux-stencil interactions.

Understencil wiping has gained increased interest over the past several years. Changes in circuit design due to miniaturized components and highly dense interconnects have increased the importance of stencil cleanliness, both inside the aperture wall and on the seating surface of the stencil. A technology that wets the understencil wipe with a solvent-based cleaning agent is being studied to improve print performance and better understand the behavior of flux-stencil interactions. The cleaning agent dissolves the flux component of the solder paste to improve solder ball release from the stencil’s bottom side and aperture walls.

Kyzen and Indium performed a study to characterize the relationship between wipe processes and bottom-side stencil flux/paste flow. A highly dense circuit board and a stencil with nanocoating was used to study the effects of the understencil wiping process. After each print, the stencil was removed from the stencil printer. The apertures were examined to inspect buildup in both the apertures and bottom side of the stencil. FIGURE 1 shows the flux vehicle and some trace solder balls following the first print.

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Realizing advanced electronics with the world’s smallest packages. 

Is it worthwhile to design printed circuit boards with the smallest component package available today: the 008004? And how do you do it correctly?

Several months ago, a hardware engineer in a high-tech company that is developing virtual reality headsets approached me. “These are special glasses that can integrate into game consoles in hundreds of millions of homes worldwide,” he said with excitement. “This is innovative technology that will enable a totally different viewing and gaming experience than what’s available at present.”

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A decade in, IPC-2581 Consortium members say the pursuit toward widespread adoption of the vendor-neutral standard was well worth the rigorous effort.

Few engineers working in electronics manufacturing today predate the first efforts to develop and implement an industry-wide standard for intelligent electronics data transfer.

As early CAD tools were introduced in the late 1960s and early 1970s, IPC launched a vendor-neutral effort to describe electronics design data from schematic through test.

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