Owens Design partnered with Questar Products International to develop a line of automatic wire bonders built on Kulicke and Soffa’s former Hybrid bonder platforms. Capabilities include fine pitch, large table travel and ball bumping, with user friendly, customizable software. The Questar Q2100 series bonders are designed for a range of complex devices.
John Apgar, president of Owens Design, said, “Our customer challenged us to come up with a cost effective design, replacing and upgrading older technology components, solving difficult electronics layout challenges, while packaging the system and all electronics in a very small footprint, and conforming to all SEMI and CE standards.”
Speedline Technologies will unveil several new options for its MPM Accela printer as well as an upgrade of its MPM UltraPrint 2000 printer at Apex 2006.
Speedline will also showcase its MPM printing, Camalot dispensing and Electrovert soldering and cleaning solutions in booth #1207.
For its parallel processing MPM Accela system – designed high-volume throughput with high yield – the company will introduce: · A High Speed Inspection option capable of full 2-D inspection of the substrate and/or the stencil at line speed. Built off the patented texture based algorithms and conventional 2-D methods, the option will quantify the inspection results and report them to SPC for process control and decision making. · An option for process setup verification and traceability using bar code reading capability and enhancements in the machine software. Provides data management down to the board (within the panel) level in the printer. · An option for closed loop control of the printer using external inspection information.
Speedline Technologies will unveil several new options for its MPM Accela printer as well as an upgrade of its MPM UltraPrint 2000 printer . The company will also showcase its MPM printing, Camalot dispensing and Electrovert soldering and cleaning solutions .
For its parallel processing MPM Accela system – designed high-volume throughput with high yield – the company will introduce: · A High Speed Inspection option capable of full 2-D inspection of the substrate and/or the stencil at line speed. Built off the patented texture based algorithms and conventional 2-D methods, the option will quantify the inspection results and report them to SPC for process control and decision making. · An option for process setup verification and traceability using bar code reading capability and enhancements in the machine software. Provides data management down to the board (within the panel) level in the printer. · An option for closed loop control of the printer using external inspection information.
IS640-280 has a nominal dielectric constant of 2.80 at 10 GHz and a dissipation factor of 0.0028 at 10 GHz. Available in 20, 30 and 60 mil thickness configurations. Other configurations available on request.
IS640-280, IS640-333, IS640-338, IS640-345, IS640-325, IS640-320 and IS640-300 are manufactured in Isola’s Chandler, AZ, facility. Data sheets for each are available for download on the Website.
RVSI Inspection will showcase the WS-2800 Wafer Inspection System in HTL Co.’s booth, #10A-101, at the Semicon Japan show, taking place Dec. 7-9.
WS-2800 is said to provide superior yield management for defect inspection throughout post-fab processes for both standard and flip chip wafers up to 200 mm in diameter.
Defects created in the post-fab area between wafer processing and final manufacturing can negatively impact production yields and time-to-market. The inspection system locates wafer defects and classifies them to reduce process costs and improve yield.
Benefits include: high-speed surface defect inspection, 100% inspection that ensures no escapes and an integrated inspection tool for fast response to process variations.
ASSET InterTech announced a new online service that validates the accuracy of boundary scan description language (BSDL) files. These files describe the boundary-scan characteristics of semiconductor devices.
ASSET collaborated with Agilent Technologies on the development of the service. ASSET will host and support the Website on an ongoing basis. Agilent previously offered an email-based BSDL checker, which has been used over 90,000 times by chip suppliers. The new BSDL Validation Service expands on its predecessor's capabilities and is available in an easy-to-use Web browser interface.
BSDL files perform boundary scan tests or programming operations on electronic circuit boards and systems. The files are used to build a model of the unit under test to apply test patterns or programming algorithms to it. An inaccurate BSDL file can cause faulty results when boundary scan operations take place.
“Before JTAG tests can be automatically generated, the engineer has to have BSDL files for all of the devices on a scan chain,” said Alan Sguigna, VP of sales and marketing for ASSET. “So the whole process begins with BSDL files. Anything we can do to help chip suppliers verify the accuracy of BSDL files will greatly improve the testability of printed circuit boards and systems for hardware manufacturers.”
The free service is available at www.asset-intertech.com/bsdl_service.
After creating a user account and password, a BSDL file can be submitted to the tool immediately. The tool retains a history of each user's submissions and, for a limited time, it will store the results of a syntax check and any test patterns that are generated. These outputs from can be downloaded at any time.