Taking a middle ground is verboten to avoid assembly problems.

Stencil design calls for three main criteria. One, the stencil should be completely flat because it needs to evenly distribute the amount of paste on all sides of the board. Two, it should be able to control solder paste spillage. If solder paste is spilled on an adjacent pad (or ball, in the case of a BGA), it could cause a short. Three, the stencil must provide optimum stability, meaning it can be repeatedly used without any issue. This could be achieved by using framed stencils versus unframed ones.

Stencil definition and design accuracy take on even greater significance when a high-count layer board is involved. In such instances, thicker boards are used for a load board application, for example, and unlike a standard six-to-12-layer commercial board, this thicker board has 20 or more layers, with more power and ground planes. This means a different thermal profile.

Stencil accuracy has a direct bearing on the thermal profile used on such a board. A thicker board, with a number of ground and power planes, requires considerably more heat for proper soldering. Also, for the same type board, a less accurate stencil design means too much or too little solder paste deposited, resulting in opens or shorts.

When a stencil is properly designed and solder paste is correctly deposited, the result is perfect printing. Put another way, this means few to no bridges or solder issues and little touchup and rework.

Special attention must be paid to devising apertures for surface mount pads on mixed signal PCB designs – in which one segment of the board is heavily analog laden, and the other digital. An analog segment requires a lot of heavy current and grounding. A thicker 0.006˝ to 0.008˝ stencil is recommended here. The thickest stencil would probably be 0.006˝ with a ratio of 1.1:1. The ratio of 1.1:1 means 10% more paste deposited compared to the pad size, thus providing a good fillet. A good fillet means enough solder is deposited, but not so much as to create a short (Figure 1).

By its nature, the analog section is a heavily ground poured area. Since heavy current is characteristic of analog circuits, those components must have extremely solid connections, either through the component side or bottom side, or internally through the ground plane. In this instance, paste deposition is called a “solder brick” (Figure 2), which describes how efficiently paste is poured on the surface mount pad. Also, a stencil for a mixed signal board must have isolation islands created to segregate current and voltage between analog and digital circuitry.

The digital side of a board with fine-pitch devices such as BGAs, µBGAs and QFNs, for instance, is another story. This calls for a ratio for paste deposits compared to the pad size of less than 1:1: for instance, a ratio of 0.9:1, which means 90% paste is being deposited. Put another way, 10% less paste is being deposited compared to the pad because the pitch is so fine. Care must be applied here because the balls of a QFN or BGA are so close that too much paste can cause a short between them.

Step Stencils

A step stencil, characterized by its different depths, is used when the application has a considerable number of analog components on one side of the board and a lot of digital on the other side. In other words, it requires different amounts of paste dispensed on different segments of the board. It provides additional paste height in certain PCB areas, and in this case, it’s called a “step-up” stencil. Conversely, sometimes, it provides lower paste height in certain PCB areas; thus, it’s called a “step-down” stencil. In other instances, where the PCB has raised areas, a “relief step” stencil is used.

As an example of a step-down stencil, consider a board with a 0.020˝ pitch QFP. A 0.007˝-thick stencil is needed for resistors, capacitors, inductors and other passives. A step-down 0.005˝-thick stencil is then used for fine-pitch technology (0.020˝) SMT devices.

A step-up stencil is used not only for analog, but also for column grid areas (CGAs or CBGAs). For example, a 0.006˝ stencil is used for capacitors and resistors. However, a step-up 0.008˝ stencil is used for CGAs or CBGAs. The extra paste height is required to support those column grid areas because they require much more paste deposition, compared to the regular SMT components on the board.

Laser-cut step-up and step-down stencils provide ideal solutions for ceramic BGA and RF shield applications. In these cases, additional solder paste deposition is required, meaning solder paste brick height is higher. As a result, it deals extremely well with non-coplanarity issues. For instance, coplanarity typically becomes an issue when an RF shield is created using HASL, rather than gold, as a surface finish on the board (Figure 3). But it’s not that much of an issue in analog or an RF board side, because the more paste deposited, the better the solder joint, especially when digital circuitry is minimal.

Thus, ceramic BGAs are one of the applications for step-up, step-down stencils. Electropolishing and then nickel plating are recommended for those stencils to achieve a good paste release for smaller aperture sizes. This stencil costs more because more processes are involved, and electropolishing or nickel plating can mean longer turnaround time.

First-article inspection is a next critical step to verify the stencil design after solder has been deposited. At this point, a determination needs to be made whether sufficient paste has been deposited for an ideal solder joint connection. Also, first-article verification step involves paste height inspection for component pre- and post-loading. Even when component placement is completed, first-article inspection should be deployed at post-placement of components. Component pre-placement inspection is performed when there’s only solder paste on the pads to verify the correct amount of paste dispensed. However, post-placement is performed when SMT components have been placed to ensure correct placement and orientation.

In some instances, the EMS provider may take a middle ground for stencil design to minimize the probability of assembly problems. Issues arise in cases like this. Let’s say the PCB layout engineer keeps the benchmark on the digital side. Based on this design, adequate paste will be deposited on pads on the digital side of the board. But it won’t be enough on the analog side, thus creating voids.

Again, as mentioned, analog requires a 0.006˝ to 0.008˝-thick stencil, while digital needs a 0.004˝ to 0.005˝ stencil. Using the wrong-sized stencil negates the concept of step stencils – to deposit the precise amounts of paste on the analog side. Also, when taking the middle ground – for example, using a 0.006˝-thick stencil for both types – the digital side may get too much paste deposition, thus creating shorts, especially when finer-pitch QFNs or µBGAs are used.

Misregistration Causes

Paste misregistration occurs for multiple reasons. The following are the most prevalent. First, the stencil aperture opening doesn’t align with the PCB. This sometimes occurs during CAM, where the proper aperture openings are not created, resulting in paste misregistration.

Also, if a PCB layout engineer is not alert or careful, they may not view the component properly to see where paste needs to be dispensed. Therefore, a layout and design engineer has to be vigilant at reading the datasheets and reviewing the component specifications.

When special components are used, it’s not always clear as to what goes on the board and what does not, or what is masked. To design proper stencils, the PCB designer has to look carefully at the physical component to ensure aperture openings are correctly defined.

Using an unframed stencil is another possible reason for misalignment. After an unframed stencil is placed on an adapter, but before it is mounted on the printer, is where damage can occur, and human interaction creates reliability issues. Also, a cleaning process must be extremely accurate during and after printing. If a stencil isn’t properly cleaned before it is archived, paste residue may be left on the apertures.

Zulki Khan is founder and president of Nexlogic Technologies Inc. (nexlogic.com); zk@nexlogic.com.

Companies return to market with new requirements, fresh capital, and new ways to evaluate cost-of-ownership. 

Value can be defined in many ways. In a financial sense, value is how much of what you need you actually get for your money. But measuring “how much you get” is not straightforward. It’s easy to confuse cost with value. Low cost does not automatically translate to the best value. Likewise, the highest price isn’t necessarily the best value. The purchase price of a capital item is only one element of value, but it can be one that is disproportionately influential in the purchase decision. A useful automotive analogy can be drawn here.

For most individuals, a car is among the largest capital purchases, or investments, they will make. Will the cheapest car represent the greatest value? The costs of running and maintaining a car need to be taken into consideration to determine a better measure of value. Then there’s the issue of the value of the car when the owner has finished with it. Leasing companies know this because their long experience and amassed statistical data have turned whole-operational-life value into a science. It’s why the monthly lease price of different vehicles is not directly proportional to their forecourt purchase price.

In principle, the same is true in industrial capital equipment. But all too often, the potential end-of-life value of a capital purchase is not taken into account. Could it be because it’s more difficult to identify the use to which the equipment may subsequently be put? Or perhaps because there’s no guide to look up the likely fiscal worth of used equipment? The experience of most electronics assembly capital equipment vendors is that investment in new equipment is typically justified on the basis of a single manufacturing requirement or contract, or at least an identifiable operational run lasting a few months to a couple years. Equipment needs to pay for itself easily within a percentage of that period to deliver a financial return. Understandably, the shorter the identified operational run, the more critical the initial purchase price of equipment seems to be to the purchase decision. But often this is a false economy.

A few years ago, one of the industry’s leading surface mount pick-and-place equipment vendors ran studies into the equipment investment its larger EMS customers were making as a proportion of its total outlay to resource each new contract they secured. The result was usually around 2.5%. (The largest single portion of every contract investment was the procurement of components.) Within a typically conventional SMT assembly line comprising printer, placer and reflow oven, the placement machines invariably represent the largest part of the investment – accounting for around 1.5% of the 2.5%. Allowing for the oven, this means less than 1% of the total investment goes toward the screen printer. At less than one-hundredth of the overall investment funding, a few percent variation in the purchase price of a screen printer is relatively insignificant compared to what return the right equipment can deliver – or the horrors of what it may cost if it doesn’t deliver.

Which is why, for these large EMS companies, the value of the printer – measured in terms that include less tangible elements like on-time delivery, service support responsiveness, applications expertise, fast ramp to productivity, maximized uptime, etc. – is always more critical than the initial machine cost.

Not all screen-printer users are large EMS providers after lucrative new contracts. But all manufacturers can improve printer ownership value by considering a few strategic points when specifying the equipment.

‘Flawless balance’ challenges. Screen-printer productivity is a combination of throughput and yield. Conveying the maximum number of good printed boards from the print platform to keep downstream processes operating at peak efficiency is the productivity goal. But getting a flawless balance between throughput and yield is a challenge; there’s no point in speeding the print process if yield suffers. Screen printing still has the most potential of any process in the assembly line to introduce catastrophic faults.^1,2 A single unprinted pad, if undetected, can render a subassembly useless or incur significant cost in diagnosis and rework. Or both.

The temptation to ramp throughput by, for instance, reducing cleaning cycle frequency or increasing squeegee excursion speed can lead to lower yields as the process moves out of control. So many variables influence the process that deploying expert knowledge is the best way to keep control. Dr. Ron Lasky of Dartmouth College, a leading Six Sigma process expert, illustrates aspects of process control in the screen-printing domain using a fictional process expert (“The Professor”) who investigates manufacturing issues, and who – as a profit sleuth – often focuses on COO as he helps electronics assemblers recover lost profit.
In one of The Professor’s investigations,³ Dr. Lasky cites the overall losses incurred by a manufacturer from switching to a cheaper solder paste. The production engineering manager’s expectation is to save more than $30,000 per line per year by using paste costing only 5 cents per gram, as opposed to 8 cents per gram.

But the paste has one property weakness in the form of lower on-screen open life, so each board printed after a stoppage must be cleaned and reprinted because the paste has “stiffened” – an exercise that costs 20 minutes in lost production per line per day, and which, with the production run figures in the example, results in a cost burden of over $340,000 per year. It’s presented as fiction, but the impression is that it’s not. In any event, it illustrates exactly the kind of process variable that requires specialized expertise to fully evaluate and manage.

Operational cost-of-ownership. Another obvious way to reduce, or at least contain, the cost associated with running a screen printer is to ensure the system is paying its way all the time – or as close to that as is practical. Downtime is the enemy of productivity. And productivity often relates directly to profitability.

Downtime comes in many forms, most predictable and therefore manageable. Even unscheduled stoppages often result from operator oversight or error, or from a process or material issue, and in theory can be legislated against.

Scheduled stoppages for consumables replenishment and planned downtime for maintenance are both areas worthy of scrutiny. Choosing a printer that has fewer maintenance intervals, or that offers easier access to permit maintenance to take place faster, will render it offline for less time, which equates to better value when measured in terms of productive uptime. Solder paste replenishment is a frequent and necessary intervention, so rapid and easy access to the print area that lets this procedure take place more quickly has a true value that reduces COO by keeping the printer productive.

In addition, simple actions like selecting the optimum consumables for production needs can improve productivity. A recent study of understencil cleaning fabrics reveals not only measurable differences in the cleaning effectiveness of materials, but disparities in the length of the fabric rolls for a given price.⁴ Naturally, the longer the roll, the less often the printer will need to halt for replenishment. Equipment manufacturers may offer a number of equipment options on printer platforms that mitigate stoppages, from effective cleaning fluids, fabric rolls and operator alerts to sophisticated tools such as paste height monitors and high throughput understencil cleaning.

The latter is a case in point on the issue of cost versus value. Newer generation systems have cleaning excursions that take half the time, use less than half the quantity of understencil cleaning fabric, and clean more effectively than comparable systems. They offer a choice: clean to the same standard as before, which means less frequently but more quickly to dramatically increase batch throughput by reducing the number of times the printer halts for a cleaning cycle and shortening the time it takes when it does; or clean as frequently as before, but twice as fast, to really safeguard yield and increment throughput. Clearly, both strategies have a tangible productivity value.

Another constraint on maintaining productivity is in high-mix assembly environments with high product changeover. Identifying ways to reduce the time it takes to set up the printer for a new board is key to productivity when measured over several batches, a more realistic snapshot of production. Using The Professor’s technique of calculating potential earnings when the printer and line are running to capacity determines revenue lost for every minute of downtime. Again, tools exist to assist. Small EMS providers and OEMs that run several products in short batches should look at automated tooling for board support; at self-loading and aligning stencils to speed the operation and eliminate operator errors; and be aware of the time it takes to upload or initialize the software print file.

Looking at these stoppage types prompted Dr. Lasky to articulate how a simple cocktail of screen-print process considerations can reverse an expected financial outcome. The example is a manufacturer who contemplates deploying new screen printers with a purchase price $20,000 lower than those traditionally in use onsite; the intention being to save a total of $1 million over 50 lines. The Professor’s investigations reveal how tiny time-based procedural issues that appear insignificant on their own can wipe out capital equipment purchase savings. In the example, factors such as 10% longer changeover due to more steps in setting up board support, computer programming and stencil installation, plus 15% more time to replenish solder paste, result in 3% less production, producing 3% less product, which equates to 6% less profit. On lines intended to average $4 million per year in profit, the small stoppages accumulate to lose around $240,000 per line per year, making the $20,000 saving on purchase price a gigantic false economy.

A final COO domain has traditionally remained unfulfilled. Arguably one of the greatest potential COO gains to be made is in the ability to redeploy a screen printer from production runs to other uses. Thanks to platform concepts, screen printers can be redeployed, often with no more than a modest investment in a module to reduce cycle time by two seconds, or an inspection system for traceability and higher yields.

References

1. J. Pan, et al., “Critical Variables of Solder Paste Stencil Printing for Micro-BGA and Fine Pitch QFP,” IEEE/CPMT International Electronics Manufacturing Technology Symposium, 1999.
2. K. Feldmann and J. Sturm, “Closed Loop Quality Control in Printed Circuit Assembly,” IEEE Transactions on Components, Hybrids and Manufacturing Technology, Part A, vol. 17, no. 2, 1994.
3. R. Lasky, “ ‘Paste is Paste’: The Professor Hits the Road,” Circuits Assembly blog, Oct. 25, 2009.
4. C. Ashmore, “Understencil Cleaning’s Little Devil,” Circuits Assembly, August 2009.

Trevor Warren is Americas product manager at DEK (dek.com); twarren@dek.com.

Although final performance is measured in the time domain, a detour may be the faster route to a signal integrity solution.

Do you speak frequency domain? Especially if you are a digital designer, you should consider learning the language of the frequency domain. The time domain has special significance because it is the real world. This is the domain in which we live our lives, where we build our intuition, and where we measure digital performance. If the time domain is the real world, why would we ever want to leave to enter the frequency domain?

For signal integrity problems related to lossy transmission lines, working in the frequency domain can often help us find solutions to eye closure problems.

Sometimes, taking a detour through the frequency domain can bring an acceptable answer more quickly than staying in the time domain.

In this brief introduction to solving problems in the frequency domain, we will look at how to improve signal quality in high-speed serial links like PCI Express (PCIe) by speaking the language of the frequency domain.

Rise time in the frequency domain. If the time domain is the real world, what does this make the frequency domain? The frequency domain is not the real world; it’s a mathematical construct. As such, it has certain very special rules that must be followed. One rule is that only sine waves can be used to describe signals.
Each sine wave is described by a frequency, an amplitude and a phase. While the phase of a sine wave is important, we usually focus attention on the amplitude of the sine wave.

Any waveform in the time domain can be translated into the frequency domain using the Fourier Transform. While it is important to have done a Fourier Transform by hand at least once in your life, after that, it’s usually more important to get the answer as quickly as possible. Every version of SPICE can perform a Fourier Transform of any arbitrary time domain waveform.

The hidden assumption with these translations, typically called a Discrete Fourier Transform, or DFT, is that the waveform in the time domain is repetitive. The repeat frequency is either the clock frequency or the total simulation time. The repeat frequency has special significance. It is the lowest frequency that will appear in the spectrum and is called the fundamental frequency.

Every frequency component that appears in the frequency domain is a multiple of this fundamental and is called a harmonic. The collection of all the harmonic components is called the spectrum.

A very important waveform in the time domain and the frequency domain, to which most other waveforms are compared, is an ideal square wave. In the time domain, an ideal square wave has a zero psec rise time and a 50% duty cycle.

Its spectrum has three important features:

• Only multiples of the fundamental appear.
• The harmonic of each component drops off like 1/n, the harmonic number.
• The even harmonics, i.e., 2d, 4th, 6th, etc., have zero amplitude.

For an ideal square wave, the frequency components continue with their pattern to infinite frequency, always dropping off inversely with frequency or harmonic number. But, if the rise time is finite, this is not the case. After some frequency, which we call the bandwidth, the amplitudes of the frequency components drop off much more quickly than 1/f for an ideal square wave.

Figure 1 shows a 1 GHz ideal clock square wave spectrum and the spectrum of a clock with a rise time that is 5% the clock period. The relationship between the 10-90 rise time, RT, and the bandwidth, BW, is roughly approximated as BW = 0.35/RT. For this example, we would expect the bandwidth to be about 0.35/0.05 = 7 GHz. This is about where the amplitude begins to drop off below the ideal square wave spectrum.

Every frequency component of an ideal square wave is significant in contributing to that 0 psec rise time. However small the amplitude may be at very high frequency, it is still important. Remove any and you won’t get the 0 psec rise time.

When the frequency component of a real waveform has an amplitude significantly smaller than the equivalent ideal square wave, it won’t be large enough to contribute to the rise time and can be ignored. The bandwidth of a real waveform is the highest sine wave frequency component that is significant. Decrease its bandwidth in the frequency and its rise time in the time domain will increase.

A fundamental measure of the rise time of a signal in the time domain is the frequency at which the harmonics begin to drop off more quickly than 1/f. For this reason, the bandwidth is often referred to as the knee frequency. The lower the knee frequency in the frequency-domain, the longer the rise time of the signal in the time-domain.

Signal propagation on real interconnects. How do real interconnects like traces on a circuit board, or coax or twin-ax cables, affect signals? In the time domain, we can evaluate the behavior of a single bit as it propagates down a transmission line. Figure 2 shows what a single 1 bit would look like traveling down a 0.003˝ wide FR-4 transmission line for a 1 Gbps signal, initially, after 30˝ and after 60˝.

The single 1 bit starts out with a 1 nsec unit interval, and a very fast rise time. As it propagates down the transmission line, the wave form is dramatically affected. That single bit spreads out into adjoining bits. This cross talk between one bit and other bits is called inter-symbol interference or ISI. It contributes to the collapse of the eye. Figure 3 shows the received eye of a pseudo random bit stream (PRBS) signal at the three locations above.

How the single bit spreads out is a very important metric of the behavior of the interconnect. Yet, as viewed in the time domain, the exact shape of the pulse is complicated and difficult to describe in a simple way.

Here is where the frequency domain description offers a simpler description. The term that describes how a sine wave differential signal is affected by an interconnect when it exits is the differential insertion loss, sometimes referred to by its S-parameter designation, SDD21. This is also called the transfer function of the interconnect. This measureable property describes what a sine wave with amplitude of 1 looks like when it comes out the transmission line. The differential insertion loss for these interconnect paths is shown in Figure 4.

Every single interconnect has a similar SDD21 response. The amplitude coming out is always less than the amplitude going in, and the amplitude of SDD21 drops off with increasing frequency. On a log scale of amplitude, measured in dB, the differential insertion loss generally drops off nearly linearly with frequency. A metric of the dB/inch per GHz is one single number that characterizes most interconnects.

If we send an ideal square wave signal into a real interconnect, its spectrum will be multiplied by this transfer function. The SDD21 tells us how each frequency component will be attenuated. Higher frequencies get attenuated more than lower frequencies. This pushes the knee frequency of the signal’s spectrum to lower frequency, and increases the rise time of the signal.

This frequency-dependent attenuation of typical interconnects will cause rise time degradation, which will smear one bit into adjacent bits, result in ISI and cause collapse of the eye.

It’s not the attenuation of the interconnect that degrades the rise time; it is the frequency dependence of the attenuation. After all, if we take all the frequency components and just attenuate each of them the same amount, we will still have the same spectral shape of the bit sequence coming out. The frequency at which the knee occurs will be unchanged; the rise time of the signal will be unchanged, and there will be no ISI and no collapse of the eye.

Fixing the eye collapse in the frequency domain. We can fix the ISI in real interconnects by either flattening the insertion loss curve of the interconnect, or by changing the spectrum of the signal going into the interconnect so that when it comes out, it preserves the 1/f shape.

Designing an interconnect with a flatter response is tough. The root cause of the frequency-dependent loss is the combination of the skin depth dominated copper series resistance and the laminate material dielectric loss. For example, certain Gore cable assemblies use a very thin signal conductor, which has a frequency-dependent resistance much flatter than a typical copper core cable.

Likewise, laminates such as Rogers’ RO4350 have a lower dissipation factor and a flatter response dielectric loss curve. Both these interconnect design features reduce ISI with a flatter differential insertion loss response.

It is also possible to flatten an interconnect’s transfer function by adding some extra frequency-dependent gain at the receiver. If the interconnect has more attenuation at higher frequency, why not add gain that increases at higher frequency to compensate and flatten the overall response? Figure 5 shows how this works.

When we add frequency-dependent gain, we equalize the response of the interconnect across a wide frequency range. We call this process equalization. The ideal equalizer has a gain curve that is the exact inverse of the attenuation curve. With a flat response, the spectrum of the transmitter is preserved at the receiver; the knee frequency is the same as the transmitter; the rise time is the same, no additional ISI and no additional collapse of the eye.

Finally, the spectrum of the signal at the transmitter can be pre-distorted to add extra high-frequency components. The interconnect will attenuate the high-frequency components anyway. If we add extra high-frequency components at the transmitter, by the time they travel through the interconnect, they will be attenuated away, leaving the 1/f spectrum of a short rise time signal. The shorter the rise time, the less the ISI, and the lower the eye collapse.

One way of implementing adding high-frequency components is called pre-emphasis. Wherever a 1 bit begins, extra energy is added. Likewise, we could obtain the same pre-distorted spectrum by taking out low-frequency amplitudes. Whenever there is a string of more than one bit with the same value, reduce the signal level. This is called de-emphasis (Figure 6).

Both pre- and de-emphasis result in the same distorted shape in the transmitted signal spectrum. When either of these distorted signals travel through an interconnect, if optimized for the interconnect, the signal will come out the other end with a short rise time, less ISI and a more open eye.

By looking in the frequency domain, we can see how the techniques mentioned manipulate the frequency domain spectrum of the received signal. We engineer it to look more like an ideal square wave’s spectrum and recreate the shortest rise time to minimize its ISI and keep the eye open so that each bit can be detected as its true 0 or 1 value.

Even though final performance is always measured in the time domain, sometimes detouring through the frequency domain may be a faster route to a signal integrity solution.

Au: Many of the principles described in this paper are covered in great detail in papers that can be downloaded from bethesignal.com.

Eric Bogatin, Ph.D., is a signal integrity evangelist with Bogatin Enterprises (bethesignal.com); eric@bethesignal.com.

Our newest columnist seeks to expose the synergy of fabrication, assembly and end-use.

Hello! I’d like to take a few moments to introduce myself, though I feel like I have known most of you for years. I have the opportunity to write this column as a result of my predecessor, John Swanson, moving on to smaller and more expensive things. John has taken the task of expanding our business to include electronic packaging. After 10 fast-paced years in the industry, I now find myself managing a business unit.

A little about me. I love yoga. It never allows my mind to travel to the pressures or issues encountered in life. But what I enjoy most is that I usually feel like a superhero after the class is completed. This last time, though, there was a new instructor, who began the class by saying, “Tonight we are going to concentrate on the basics.” Great, I thought. How can I reach superhero strength if we are going back to the beginning?

Yet, I left an extremely sore and beaten woman. Not only was I a better person than the one who entered, but I had my idea for this column: How can we expect greatness if we do not pay attention to the basics?

It’s cliché, but building a strong foundation paves the way for success in everything we do. Consider process control. Again, I know part of you is cringing, but there is another side that remembers the last three product issues experienced came down to poor process control. Ensuring good control will result in the best possible products we can make.

Did you know that when the board goes through the reflow oven, if vias are not properly plugged with soldermask, the mask cracks, leaving exposed copper? As in Figure 1, the copper found through the crack has not seen any protective coating and becomes a breeding ground for corrosion. If soldermask registration is off on a pad, and the solder cannot collapse properly, the resultant joint is more susceptible to thermal fatigue.

Imagine a BGA pad that has one side soldermask-defined, as a result of misalignment, and the other metal-defined. The solder collapse will not be uniform. During reflow, the soldermask will expand on the one side, creating pressure on the sphere, which acts as a lever. This can promote joint cracking.

Inadequate copper preparation will result in nonuniform coverage of an OSP coating. This is true for all surface finishes, though shortcuts often are taken at the cleaner and microetch steps of a process. If the copper surface has contaminants, the finish will not properly bond to the copper. This can manifest itself as nonuniform coverage, poor surface coating adhesion, insufficient thickness, solder joint voiding, and even premature tarnishing.

Also true for any surface finish is the importance of coating thickness. Believe it or not, thickness specifications were put on the technical datasheets for a reason. The specified thickness is critical to the coating’s performance. Everyone has experienced an insufficiently plated tin deposit. After one reflow, all the pure tin had been quenched by intermetallic that laughed at you on the second assembly pass.

Focusing on process flow and routine analysis can eliminate many future quality issues. Did you know sending a board twice through Pb-free HASL can embrittle the soldermask to the point where the resultant product will have much worse creep corrosion than any thin immersion silver deposit? Did you know the first instance of soldermask interface attack on an immersion silver board was found as a result of a customer continuously dragging microetch into the following rinse, which did not have a sufficiently strong turnover? Basically, the PCBs were being double-etched, and then put directly into the pre-dip bath.

On a positive note, running the right process controls can make a better product. Choosing the proper equipment for immersion tin can minimize solution air exposure and extend bath life. Premature tin oxidation and thiourea decomposition can be greatly reduced. Using the right pre-clean, including a well-maintained microetch, can enhance the OSP and immersion silver coating quality, which in both cases enhances solderability.

Maybe you do realize all this. But did you realize how much research at a chemical supplier goes into widening an operating window to accommodate the “what ifs” in fabrication? It is amazing what is asked of the surface finish on a day-to-day basis.

I don’t want this to be a finger-pointing exercise. I want to provoke thoughts on how to make process control second nature. I want to expose the synergy of the fabrication, assembly and end use performance. Every detail affects the next step and ultimately the final product.

When I started on this journey, I learned quickly that there was an application for each surface finish. They all have strengths and weaknesses. If processes are run according to specifications provided, and the same can be said for the processes around them, the resultant product will be superior. There are many instances where a coating outperforms the expectations of the chemical supplier, fabricator assembler and end-user. Imagine a surface finish produced as a result of everything run under optimal conditions: superhero status.

Lenora Toscano is final finish product manager at MacDermid (macdermid.com); ltoscano@macdermid.com.