Research continues on improving printed frontside silver conductor line efficiency.

A simple Internet search will reveal the photovoltaic industry is working hard on higher aspect ratio frontside conductor grids as a route to greater solar cell efficiencies. This is because the conductors, typically screen-printed on a cell’s frontside, block sunlight from reaching the energy converting strata below, and the narrower they are, the less shadow they cast.

However, as it is essential they maintain their current carrying capacity, and as this is governed by their cross-sectional area, it follows that as their width decreases, their height must increase. Hence the need for a greater height/width ratio, or aspect ratio.

While the pursuit of higher aspect ratios is essential, this goes hand-in-hand with an equally important factor that until now has been largely overlooked: conductor uniformity. This will become a critical factor as feature miniaturization progresses, as a conductor with many high/wide and low/narrow points is less efficient than one that has the same cross-section throughout.

A team here has been conducting in-depth studies on this issue since 2008, with the aim of developing a method for improving the efficiency of printed frontside silver conductor lines. Recently, results of this ongoing work were presented at the 24th European Photovoltaic Solar Energy Conference in Hamburg.

As part of the study, the team looked at the relative merits and demerits of printing using conventional mesh printing screens versus two-layer electroformed nickel stencils, carrying out extensive tests on both to identify the features necessary for an optimized, high-aspect ratio printing process.

They also explored in detail a significant obstacle to achieving the improved levels of paste transfer efficiency required for higher aspect ratio conductors when printing with conventional mesh screens: The screen apertures are partly full of wire. The first problem is the volume of screen aperture occupied by the wire cannot be filled with paste; and, second, the wire presents a large surface area to which paste can stick instead of transferring to the wafer.

Indeed, when analyzing conductor structure, it was graphically clear that the intervals between the highs and lows in any conductor mirrored the intervals between the knuckles in the screen mesh.

Much has been done to mitigate this problem. Wire diameters have been reduced to a current industry standard of 20 to 25 µm, and this has greatly improved aspect ratio and conductor uniformity. However, there is a limit to how fine a wire can be used, especially considering a screen must be sufficiently robust to withstand 10,000 sweeps of a high-speed, high-pressure squeegee. There is also a cost issue: Fine, high mesh-count screens are more expensive than large diameter, low mesh-count screens.

One obvious solution is to remove the mesh from the apertures completely, and several successful attempts already have been made to do just that using two-layer electroformed stencils. Our team decided to explore this option using a number of high-precision, two-layer electroformed nickel stencils designed especially for the tests.

Two-layer stencils typically use a bottom nickel aperture layer in which the wafer pattern is formed. This is protected and stabilized by a top layer, which, in its coarsest form, is a simple perforated foil. Such stencils provide much improved paste transfer and conductor uniformity over mesh screens, but improvements can be achieved by replacing the standard perforated foil with one that has reinforced apertures similar to, and that correspond with, those in the bottom layer. Here, the challenge lies in precisely aligning the two layers, and in ensuring the apertures are well-engineered.

Using appropriate pastes and this more sophisticated approach to stencil design, improved aspect ratios were achieved, as line widths were decreased to 50 µm and conductor uniformity was significantly better than anything realized using mesh screens.

Given these results, the team noted two-layer metal stencils could potentially outperform the best emulsion mesh screens, but that several obstacles must be overcome before this technology can be implemented widely. First, whereas the photoimageable emulsion used for mesh screens is sufficiently elastic to provide a reliable gasket between the screen and the wafer’s textured surface, the bottom layer of a nickel stencil is unyielding and could cause silver paste to bleed, creating more problems than are solved. Also, the stencil’s bottom surface must be totally defect-free; nickel nodules could crack or even break the wafer as pressure is applied. Such stencils are also more expensive, and their use in high-definition work requires a high degree of technical skill.

Having said this, electroformed stencils do provide relatively open apertures. This, and the considerable advantages of mesh screens, led the team to develop a third option: a hybrid solution based on a conventional screen, but that replaces its wire mesh with a prefabricated electroformed nickel top layer with reinforced apertures similar to those used in two-layer electroformed stencils. This is coated on the underside with traditional photoimageable screen emulsion, enabling the team to maintain the ”soft contact” gasketing properties of screen emulsion while freeing the apertures considerably.

Details regarding a hybrid screen solution were presented at the Hamburg event. This hybrid technology is effectively a printing screen with almost no metal in the apertures that, once its design is optimized, should offer better paste transfer efficiency, aspect ratio and cross-sectional area uniformity than the alternatives from which it is derived.  CA

Tom Falcon is senior process development specialist at DEK (dek.com); tfalcon@dek.com.

Several devices perform well under vibration and temperature cycling testing.

We recently characterized the reliability of surface mount RF components. The RF frequency band of interest was the X band (10.7 to 11.7 GHz). A two-pronged test for printed circuit assembly reliability was designed for both extreme thermal cycling and vibration. The rapid thermal cycling and extreme vibration testing simulates the total stress encountered by the assembly over the life of the product, but accomplishes it in a relatively short period of time. To perform the reliability testing, a test vehicle consisting of a printed circuit board with test structures and components was designed, fabricated and assembled onsite.

The surface mount technology components selected were commonly used and have operating ranges up to the X band of the RF spectrum. A digital attenuator in a quad flatpack, no-lead (QFN) package was used with supporting chip components in 0402 and 0603 sizes. Two surface mount hybrid couplers with different leads were installed: one with L leads and one with castellated leads. Side launch SMA connectors with through-hole ground connections were installed to permit connection to the spectrum analyzer.

The frequency range of the attenuator is up to 13 GHz, while the other RF components are less than 4 GHz, based on their application in the actual circuit.
The test vehicle was designed to simulate a proposed board stackup and permit the mounting of the SMT RF components. Each board has six RF paths that pass through the components (Figure 1). To observe any effects of vibration and thermal cycling on the laminated board, three RF paths were designed with no components to act as controls.

Component manufacturer’s data sheets were used to define the shapes and sizes of both the pads on the CCA and the cutouts for the solder paste stencil. The stencil thickness was 0.005˝ to permit the proper solder volume on the 0402 and 0603 component ends. The larger, castellated lead coupler required a stencil with a “window pane” feature to reduce the volume of solder used to solder the large center ground to the ground plane.

The solder paste selected was the type typically used for military assemblies (SnPb37 with a no-clean flux and a J-STD-004 classification of ROL0). The board layout was programmed into a pick-and-place machine so the QFN and 0402 components could be placed accurately. A double-reflow process was used. All flux residue was removed using an inline cleaner to meet IPC-A-610 Class 3 requirements.

Accelerated testing plans. Component reliability was tested using accelerated temperature cycling based on JEDEC Standard JESD22-A104. The assemblies cycled between +85°C to -40°C for 1,000 cycles of 91 min. each. Breaks for RF testing occurred at 100, 200, 400 and 1,000 cycles to permit more resolution into the possibility of early thermal failures.

Vibration testing also was performed to simulate the stresses of motion on the components over the assembly’s life. The three axes vibration testing was performed for two hours at frequencies from 4Hz to 50Hz per MIL-STD-167 Type 1. The test vehicles were RF tested prior to being sent for vibration and then RF tested again on their return to the EMPF.

Thirty test vehicles were assembled using in-house SMT equipment. Prior to thermal cycling and vibration testing, each of the RF paths on all the assemblies was visually inspected and swept for transmission loss (S21) and insertion loss (S11) to gather baseline data. An Anritsu Spectrum Analyzer was used and data were gathered from 40 MHz to 20 GHz.

Fifteen CCAs were sent for thermal cycling and 15 were sent for vibration testing. After vibration testing, there was no evidence of cracked solder joints or other evidence of stresses between the devices and the board. The RF paths on each of the 15 assemblies were swept, and data showed no significant degradation in the device or path performance (Figure 2).

Fifteen CCAs were run through 1,000 thermal cycles with visual inspection and RF testing performed at established break points. Again, no evidence of damage was apparent on the visual inspections, and no significant degradation in performance was apparent on any of the CCAs after RF testing (Figure 3).

The analysis showed no significant degradation of performance. Visual inspection of the components and solder joints showed no physical damage and almost no degradation in performance through the accelerated life tests (Figures 2 and 3). Although the figures shown are for one specific device through the tests, all other SMT components performed as well.  CA

ACI Technologies Inc. (aciusa.org) is the National Center of Excellence in Electronics Manufacturing, specializing in manufacturing services, IPC standards and manufacturing training, failure analysis and other analytical services. This column appears monthly.

Don’t let the accountants sign their own checks.

We have heard scores of times the call to participate and spend time for the greater good of something. When it comes to human catastrophes, everyone drops their pencils and quickly understands the principle of prioritization. The fight for someone’s life or livelihood clearly comes before internal deadlines or sitting on a committee a few times a year.

Today’s “tragedy” is that we are bombarded with emails and daily internal and external correspondence, while trying to finish our regular responsibilities. Globalization has done its fair share: It allows us to focus on what is most important for our companies, which generally is a good thing. As a result, however, many companies do not allocate sufficient staff and resources for things other than just day-to-day work.

It is here where I think the mistake is made. It is difficult to see beyond one’s current and daily set of responsibilities; plan strategically and visualize the bigger picture and, thus, greater good. Let me explain.

When it comes to volunteering time and resources, there are always the “10-percenters”: i.e., those who always stand ready to help. Working for and with IPC, an internationally recognized body, however, requires all of us to participate, regardless of location. This is my call for help! It is meant to recruit more participation as, at the end of the process, we all benefit from the published standards. A standard is merely an established norm or requirement documenting uniformly recognized and accepted criteria, methods, processes and practices. For those currently working below these norms, a significant benefit suddenly emerges as standards provide guidance.

Over the years within our organization, we have coined the term “borderless engineering.” It symbolizes the power of local, yet global knowledge and expertise. We have chemical engineers all over the world, and we recognize the value of the internal sharing of local engineering expertise to create a global knowledge database. Upon implementation, we became better equipped to assist each and every customer. Yet, at the beginning of this process, had I asked an engineer in Germany or China to volunteer their time to sit on a committee, I think I would have had a hard time explaining the bigger picture to them. They might have found numerous reasons why it would have not been worth the time. But by letting go of our self-interest and domestic focus for a second, we have come to realize how some things pay off in the long run.

A few weeks ago, I participated at the IPC Winter Interim Standards Development Meetings in Arizona. Unfortunately, I did not see enough active members present during the cleaning handbook session. This lack of participation could have been simply due to most people’s general aversion to chemistry; but, on further thought, it was probably due to the economy and maybe a matter of priority. Encouragingly, some members did take advantage of calling in to our “go-to” meeting. On a positive note, we did not witness the often-seen “drive-by-crowd”: those who come once, participate with vigor, and then forget about future meetings.

The low turnout should serve as a warning to everyone. I purposely chose the word “warning,” as the impact of insufficient attendance cannot be overstated. For one, this set of handbooks is revised every 10 years, and much can and does happen in a decade. Customers, engineers and vendors not present at the time consequently have no input and run the risk of not being heard or included. Afterward, the process engineer must adhere to the published “industry accepted” guidelines, which they could have actively created.

Second, each handbook also undergoes a process called peer review. It was established to promote objectiveness during the adoption of an industry standard. As the peer review is one of the final steps prior to publishing, it is only as valuable as the participating group. Key subject experts are needed to add critical substance. The smaller the group becomes, the more it mirrors the scenario of accountants signing their own checks; thus, the quality of the overall manual/handbook is at stake.

I believe you now understand the moral of this column. There are larger things in life and this industry worth the effort and participation. While your time will not be compensated directly, your company will benefit in the future from the expertise and input of other companies and engineers who know things you may not.

Take advantage of this tremendous opportunity. I personally look forward to our next IPC standards meetings at Apex next month.  CA

Harald Wack, Ph.D., is president of Zestron (zestron.com); h.wack@zestronusa.com. 

Paste stuck in stencil apertures led to poor wetting during reflow.

The optical image in Figure 1 shows a side view of a chip-scale package with open joints. The gold pads did not wet during reflow soldering. Close examination showed the process was out of control, with poor solder paste printing, leading to pads not covered with paste. During process review, solder paste was found hanging up in the stencil apertures. With no paste, there also would not be any flux medium to aid reflow in an air environment.

It is possible that if the balls, pad and a nitrogen environment were used, reflow and wetting may have occurred, masking the root cause of poor printing. In fact, the problem is related to poor printing. This may be due to the design of the pad or stencil, poor printing parameters or blocked stencil apertures. The process needs to be reviewed and corrective action put in place. In-process inspection and training also may be beneficial.

These are typical defects shown in the National Physical Laboratory’s interactive assembly and soldering defects database. The database (http://defectsdatabase.npl.co.uk), available to all this publication’s readers, allows engineers to search and view countless defects and solutions, or to submit defects online.  CA

Dr. Davide Di Maio is with the National Physical Laboratory Industry and Innovation division (npl.co.uk); defectsdatabase@npl.co.uk. His column appears monthly.