Identify and solve placement and reflow-related solder defects.

We continue our series on solder bridging. This month, we look at potential problems caused by the placement machine and reflow profile.
If the pick-and-place machine is suspected:

Problem: Placement inaccuracy narrows gap between pads, increasing the chance of bridging.
Recommendations:

• Verify component placement pressure.
• Use x-ray to verify BGA placement.
• Use microscope for QFPs.

Problem: Excessive component placement pressure will squeeze paste out of pads.   
Recommendations:

• Verify actual component height against data entered in the machine.
• Component placement height should be ±1/3 of paste height.

If the reflow profile is suspected:

Problem: Extended soak will input more heat to the paste and result in paste hot slump phenomenon.
Recommendation: Adopt a straight ramp to spike profile, without soak zone if possible.

Paul Lotosky is global director - customer technical support at Cookson Electronics
(cooksonelectronics.com); plotosky@cooksonelectronics.com. His column appears monthly.

Eight steps to getting the best possible test coverage.

IEEE 1149.1 for boundary scan adoption has seen a steady climb in use for the past five years. In particular, it has gained popularity with NPI test engineers working with high node count printed circuit boards for telecom network servers/switches and PC servers. There are several ways to implement boundary scan test on PCBs, the two most common being:

• Native boundary scan on in-circuit test systems. (Note: Native boundary on ICT is an integrated solution where the boundary scan test will be developed and executed within the same ICT interface. No additional third-party hardware or software is needed.)
• Standalone benchtop boundary scan. Standalone benchtop boundary scan is preferred during prototype/NPI, as it enables PCB testing without building an ICT fixture. However, it has not been adopted for high-volume manufacturing, where the majority of manufacturers use the native boundary scan on ICT. Here’s why:
• Cost. A basic benchtop boundary scan setup is about $10,000 to $20,000. Additional licenses for development, debug and runtime features will increase the cost of the benchtop boundary scan solution up to two to three times the basic cost. Compared to the cost of using native boundary scan on ICT solution, the latter is practically free, as most EMS providers and ODMs would already have boundary scan licenses enabled on their existing ICT systems, which include development and debug features.
• Separate station. Running an extra station after ICT doesn’t appeal to most assemblers, as it means extra system and manpower costs, not to mention an additional process.

There are other minor reasons, such as local support, especially for the majority of high-volume manufacturing sites in Asia. Availability of expert support from the benchtop boundary scan vendors in Asia has not come far compared with that offered by ICT vendors. This is understandable, since ICT has been around for more than 30 years in electronics manufacturing, fostering a more robust support model.

These are just a few reasons why most assemblers prefer ICT for boundary scan test for volume products. Besides, ICT offers coverage for most of the PCB defect spectrum (opens, shorts), analog components value measurements, as well as powered test, which includes voltage measurements, clock measurements, digital test and in-system programming capabilities. Table 1 compares boundary scan test coverage of a typical benchtop boundary scan setup with an ICT offering boundary native scan capabilities.    

Although native boundary scan on ICT is the preferred solution during volume manufacturing testing, avoidable implementation issues can affect stability of the test.
Boundary scan tests, like any other digital test during ICT testing, are susceptible to noise, which affects stability. As such, the following best practices should be considered:

1. Assign critical attributes to JTAG pins (TDO, TDI, TMS, TCK and TRST) to ensure the shortest wire possible (Figure 1). To ensure signal quality and fidelity, consider assigning critical attributes to the JTAG pins during test development to ensure the fixture has the shortest wire possible (as short as 1") from the ICT system’s digital card pins to the test probe. The shorter the wire on those JTAG pins, the less the possibility of an adjacent wire crosstalk.

2. Proper fixture ground plane implementation. The main objective of using a ground plane on the ICT fixture is to reduce ground loop created by the distance between the ICT system ground and the PCB ground via fixture wiring. Unfortunately, few understand proper ground plane implementation, which can make or break the ICT digital or boundary scan test (Figure 2). The objective of having a proper ground plane is to help ensure the PCB ground is as short as possible to the ICT system’s digital ground during digital test, to minimize ground loop, as well as ensure that the signal wire stays closer to the ground to minimize crosstalk. Figure 3 is an example of a badly implemented ICT fixture ground plane, which is worse than not having a ground plane.

3. Twisted-pair wiring on JTAG pins (TDO, TDI, TMS, TCK and TRST). Aside from short wiring, another strategy to ensure signal integrity and minimizing noise is implementing twisted-pair wiring on JTAG pins. Twisted-pair impedance of approximately 100 Ω matches the low output impedance of the digital driver of the ICT system, which will result in a better drive signal integrity.

4. Removing physical test probes. For nodes that have only boundary scan devices connected to them (100% boundary scan nodes), removing these probes could ensure the signal integrity on those nodes stays clean. However, use a conservative approach in removing test probes on boundary scan nodes, as it will mean losing test coverage if there are non-boundary scan devices or analog components connected to it.

5. Dual-stage fixture. Most of the designs of high node count assemblies have resorted to a dual-stage fixturing solution where during the first stage, all the test probes are in contact while executing unpowered and powered in ICT (Figure 4). At the second stage, executed after all first stage tests have been passed, the fixture probe plate will move up either mechanically or via a pneumatic cylinder to disengage most of the normal test probes, with only a few long travel test probes remaining in contact. The test probes in contact during this second stage are power, ground, JTAG pins (TDI, TDO, TCK, TMS and TRST), as well as compliance and disabling pins (Figure 5). With the dual-stage fixture strategy, most noise coupled through the fixture wires is eliminated, resulting in a stable boundary scan test.

6. Power cycling or reset sequence. Adding a power cycling or reset sequence procedure to the test plan ensures the boundary scan devices in chains are in the proper state for testing. During boundary scan, the core logic of the devices in the chain is disconnected from the rest of the board, which probably would affect other devices operating in normal mode. Other devices exchanging data with boundary scan devices will consider the devices inoperable.

Note that when the board comes out of boundary scan mode, all the boundary scan devices go into BYPASS, and the core logic is reconnected to the I/O pins, but the board and the boundary scan devices do not necessarily pick up where they left off. To get the board back to normal operating mode, the board reset procedure must be run, or board power must be cycled. This can be done by adding a reset sequence or power cycling procedure to the test plan.

For multiple chains, interactions between chains can be a problem. For problems with connect tests or disabling difficulties, try adding a power cycling or reset sequence to the test.

7. Disabling upstream device, oscillator, switching voltage regulator. When a digital or boundary scan device is being tested, its surrounding devices can affect the way the device operates. This, in turn, can affect the test for that device, resulting in an unstable boundary scan test. To some extent, the effect that other devices have on the inputs to the device under test is minimized in the test system by overdriving. However, this is not always completely effective and cannot be used with high-speed signals. Disabling the upstream devices ensures that there is no other signal interference while executing boundary scan test. Disabling on-board oscillator and switching voltage regulators ensure that noise coupled through fixture wiring is minimized, which will result in a stable boundary scan test.

8. Maintaining JTAG pins signal during boundary scan test and disable state. Most PCBA with good boundary scan design for test implementation will take care of the pull-up/down resistor of the JTAG pins to ensure stability of the boundary scan test. If these DfT factors have not been included on the board, implementing them on the fixture will help.

The TCK (test clock) should be treated like any clock pin, although it has nothing to do with the on-board clock function. The TCK should be terminated with a 68 Ω resistor in series with a 100 pF capacitor to ground.

Maintaining stable TMS (test mode select) signals, either during boundary scan test or the disable state, is very important. During boundary scan test, the test generated by ICT will ensure that TMS will maintain its level according to the state diagram. However, during boundary scan test, disabled TMS should maintain a signal level to remain in the reset state. A pull-up resistor will help to ensure that TMS remains high.

TRST (test rest) is an optional JTAG pin designed to let the boundary scan test get into the TEST-LOGIC-RESET mode regardless of the state of TMS or TCK. Whenever TRST gets asserted alternatively in the absence of TRST pins, boundary scan will enter the TEST-LOGIC-RESET mode when TMS is held high for at least five rising edges of TCK. The TRST signal should include a pull-down resistor when possible to reduce the chance the signal floats when it is not being driven by the ICT driver.

The success of boundary scan test implementation on ICT lies not only with the tools used, but also the project team’s support of the strategy from design and test engineering up to production. With a new set of boundary scan-related IEEE standards (P1687, P1581, 1149.7, 1149.8.1) expected soon, boundary scan will get a further boost in the board testing environment. 

Bibliography
1. IEEE, 1149.1-2001, “Standard Test Access Port and Boundary-Scan Architecture.” June 2001.
2. SMTA, SMTA/TMAG Testability Guidelines TP-101D, 2008.
3. Kenneth P. Parker, Boundary Scan Handbook, 3d edition, 2003.

Jun Balangue is technical marketing engineer at Agilent Technologies (agilent.com); jun_balangue@agilent.com.

Using preforms, balls can be removed and reattached in an hour.

Removing and reworking the BGA is often an economically attractive alternative to replacement with a new part. If the intent is to reuse the BGA, the solder balls must be replaced before it can be resoldered to the circuit board. The BGA removal process renders existing solder balls unusable.

Starting with a BGA removed from the board, the first step is to bake the moisture out of the component to prevent a defect known as popcorning. This defect appears as craters in the BGA package, caused by the explosive expansion of absorbed water vapor during reflow. It is easy to see on the top and sides of components, but after the solder balls have been reflowed, it can be more difficult to see on the underside of the component.

Next, remove the existing solder balls and clean the surface. Solder balls can be removed using a soldering iron with a blade tip attached. Uniform heating of the part with auxiliary heating is necessary to avoid localized thermal shock to the BGA from the hot blade. This method is adequate for bulk solder removal. Care must be taken not to scratch the BGA surface. Generous use of flux increases the effectiveness of the heat transfer and also removes any oxides. Solder braid is used next to remove smaller flecks of solder, also with generous flux.

As a final cleaning and preparation, the BGA is carefully washed with isopropyl alcohol (IPA) to remove flux. The part is then inspected. Cleanliness can be confirmed using standard resistivity of solvent extract (ROSE) or SEC (solvent extract conductivity) testing.

Specify the BGA type and part number to BGA reballing vendors in order to obtain the correct preform parts.

Continuing with a clean, solder-free BGA, the next step is to perfectly position the balls under the BGA. With hundreds of solder balls to be exactly positioned, a mechanical device is required to maintain the alignment and position the solder balls under the chip. The two most popular methods to actually attach the solder balls are the “preform” method and the “specialized fixture” method. The preform method holds solder balls in the exact pattern using a water-soluble paper carrier (Figure 1). This precise paper form is the key to this process and ensures the balls are aligned on the carrier within 0.0004".

The perimeter of the preform is precision-cut to perfectly match the BGA dimensions. Mating the preform to the BGA is accomplished by applying paste flux to the BGA (Figure 2). The paste flux is sticky, and holds the BGA to the preform. A fixture is often used to speed assembly and ensure accuracy (Figure 3).

The next step is to reflow the two mating parts using a profile based on whether the solder balls are SnPb or Pb-free. The BGA assembly is processed through the reflow oven the same way a board is processed. The solder balls are now attached to the BGA.

Then remove the paper carrier (which is designed for easy removal). After part inspection, the BGA is ready to be attached to the board.

With some experience, good equipment and a mature process, the entire rework and BGA reballing process can be accomplished within an hour.

ACI Technologies Inc. (aciusa.org) is the National Center of Excellence in Electronics Manufacturing, specializing in manufacturing services, IPC standards and manufacturing training, failure analysis and other analytical services. This column appears monthly.

The wider the diameter, the faster solder joints will form.

Selective soldering generally uses two basic nozzle design types: One is the “round” nozzle, also known as a “bullet” or universal nozzle. It can approach any solder site from any direction, since it is completely radial in its design on the top.

The other is a component-specific wave or “letter-slot” nozzle, and its design is better suited to soldering rows of pins, such as found on an array. This nozzle shape is ideal for connectors, for example, a five or a six-row connector, with perhaps 40 to 50 pins in a row. One could use a round nozzle for such a job, but that would lead to a deviation in the overall soak time in the solder, because as the nozzle travels along parallel rows of pins, the pins in the center of travel dwell in the solder for the full diameter of the nozzle, but the pins on the outer edges – the outside rows – would see only a section of the diameter, basically an arc. As such, the dwell time under solder for the pins in the center actually could be twice as long as the exposure for the pins in the side rows. This can result in a variation in quality for the solder joints in the outside rows.

That’s when we prefer to use the wave nozzle, because it is designed for the component shape we are soldering; in this case, all the rows would see the exact same dwell time, thus ensuring consistency in solder joint formation quality.

In selective soldering, it’s important to get enough heat into the solder site, as rapidly as possible, to overcome the heat sink characteristics of the board and get good wetting and filling of barrels right up to the top side of the board. Accommodate longer pins, if encountered. To do this requires flexibility in the amount of “freeboard” of molten solder – the parabolic bubble of moving solder – at the top of the nozzle. Different suppliers use different methods of achieving this, from controlling pump speed to various nozzle design factors. What we find effective is a machined radial groove near the top of the inside of the nozzle that provides universal back pressure at the periphery, so that the solder in the center of the nozzle will rise higher than it would normally if the flow of the solder column were uniform.

The concept is simple, but the effect is to provide the greater freeboard of the parabolic dome of molten solder emerging from the top of the bullet nozzle. It also permits a high rate of solder exchange; this in turn provides a high rate of heat exchange, thermal transfer to the solder site, permitting proper hole filling in the barrel, a feat often difficult with multilayer, high heat sink boards. A higher freeboard actually lets the machine “pump” solder into the holes that need complete filling; but at the same time, we want a constantly controlled solder wave or fountain shape.

A rule of thumb in nozzle selection is to always use the largest diameter nozzle available that will handle every selective soldering task on the board; don’t skimp by using a small nozzle. If a bigger one can be used, all the better; the bigger the nozzle, the more thermal energy will be imparted to the board, and also the quicker the solder joints will form, thus reducing dwell time. Try to use the same nozzle for every site on the same board, if possible.

Practically all selective soldering equipment manufacturers provide wetted nozzles, and these deliver excellent performance. With these nozzles, the outside diameter of the nozzle is actually wetted by the solder. Everyone has their own particular approach; in our case, a proprietary alloy lets us achieve this wetted effect. Wetted nozzles provide more uniformity and control of the flow of the molten solder as it travels back toward the pot.

In many cases, for expediency, uniquely shaped nozzles can be designed to solder a number of sites and multiple solder joints simultaneously, in a stamping or a branding type of operation. For example, there might be multiple nozzles of various shapes in the same nozzle manifold that come up and stamp a certain pattern time and again. They might be a mix of square, rectangular, round and half-round, etc.

When Pb-free selective soldering, remember that even stainless steel nozzles are scavenged by the tin in the solder. SnPb alloys seem to have little effect on the longevity of stainless steel nozzles, but Pb-free alloys, and particularly SAC types, will erode the nozzle material, even stainless. One remedy is to coat the inside of the nozzles with a resistant coating to prevent or at least slow that erosion process. Erosion of stainless will add nickel content to the solder pot, and any type of dissolved metals contamination can impact solder joint reliability.

Have uniform control of the “freeboard” of solder above the nozzles. However, selective soldering nozzles, particularly smaller-diameter nozzles, are notorious for gradually losing the height of the solder freeboard over time due to the buildup of contamination inside the nozzle. Real-time measurement of the solder height that will automatically adjust pump speed in order to maintain a pre-set desired height is valuable here. That’s a critical part of the process. If solder height diminishes and you aren’t aware of it, soon you’re not soldering at all, or at least not getting the desired quality.

Selection, shape, design and function of selective soldering nozzles are a critical focal point of successful soldering. Know your nozzles! Understand their features, how they affect and control the solder wave, and what their vulnerabilities may be to the specific alloy used.

Alan Cable is president of A.C.E. Production Technologies (ace-protech.com); acable@ace-protech.com.